Power boards

USB-C multi-rail power module

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

ADCIN1 ADCIN2 ADCIN3 ADCIN4 CAP_MIS_N CBOOT_1V1 CBOOT_1V8 CBOOT_3V3 CBOOT_5V0 CC1 CC2 EN_1V1 EN_1V8 EN_3V3 EN_5V0 FB_1V1 FB_1V8 FB_3V3 FB_5V0 GND PD5VMAX PD_15V PD_FAULT_N PD_I2C_SCL PD_I2C_SDA PD_LDO_1V5 PD_LDO_3V3 PD_RESERVED26 PD_SINK_EN_N PG_1V1 PG_1V8 PG_3V3 PG_5V0 RBOOT_1V1 RBOOT_1V8 RBOOT_3V3 RBOOT_5V0 RT_1V1 RT_1V8 RT_3V3 RT_5V0 USB_SHIELD VBUS_RAW VCC_1V1 VCC_1V8 VCC_3V3 VCC_5V0 VOUT_1V1 VOUT_1V8 VOUT_3V3 VOUT_5V0

Production status#

Source: boards/usb-c-multi-rail-power

Status#

Rev 0.1 schematic capture and four-layer PCB routing are complete. KiCad 10.0.4 reports 0 ERC violations, 0 DRC violations, 0 unconnected items, and 0 schematic/PCB parity issues. The 115 mm x 95 mm board has 113 footprints, 67 nets, 540 routed segments, 195 vias, and 14 zones.

The automated preflight reports 28 PASS, 5 CONDITIONAL, 7 OPEN, and 0 FAIL. Gerbers, separate PTH/NPTH drills, a qualified 81-line core-SMT BOM, pick-and-place data, checksums, fabrication ZIP, and visual-review outputs are under manufacturing/. See the detailed qa/report.html.

This is an engineering prototype release, not a production release or regulatory certification. Exact capacitor curves and physical bench/compliance gates remain open.

Purpose#

This board converts a USB-C Power Delivery input into four simultaneous, independently controlled hobby/FPGA supply rails:

The 3 A rating is per channel. The normal input contract is 15 V at 3 A (45 W), which supports all four rails at their full 33.6 W combined output only when conversion, connector, and thermal losses remain inside the verified budget.

Frozen rev-0.1 architecture#

USB-C receptacle
    -> TVS2200 positive-surge clamp + SS34 negative-transient clamp
    -> TPS25730AD protected PD3.2 sink path
       (hardware-strapped for exactly 15 V / 3 A;
        sink path disabled on capability mismatch)
    -> PD_15V protected intermediate bus
       |-> TPSM63603 -> 1.1 V / 3 A
       |-> TPSM63603 -> 1.8 V / 3 A
       |-> TPSM63603 -> 3.3 V / 3 A
       `-> TPSM63603 -> 5.0 V / 3 A

• The TPS25730ADREFR includes the high-voltage sink switch, reverse-current protection, overvoltage supervision, and resistor-strapped PD policy. It does not require an MCU, EEPROM, or production firmware image.
• Each TPSM63603RDHR contains its inductor and power switches, accepts up to 36 V during normal operation, and exposes enable and power-good signals.
• A charger that cannot provide a 15 V / 3 A contract must not power the converter tree. There is deliberately no reduced-power 5 V fallback.
• All four rails default to enabled after a valid PD contract. Each rail enable and power-good signal is exposed for external sequencing.
• A 47 uF / 25 V polymer capacitor plus the eight converter-input MLCCs form the protected-bus bank. Worst positive tolerance is 97.76 uF, below the 100 uF limit; exact MLCC DC-bias curves remain an AVL evidence gate.

Interfaces#

• One 5.08 mm two-pin terminal block per output for full-load wiring.
• One duplicate 2.54 mm four-pin header per output (two rail pins and two GND pins) for light-load breadboard work only.
• A 2x6 control header exposes each rail enable and power-good signal, the PD capability-mismatch output, master fault input, 3.3 V logic reference, and GND.
• A separate four-pin diagnostic header exposes the PD controller I2C target interface. I2C is optional and is not required for normal operation.
• Test points cover raw VBUS, protected 15 V, all outputs, CC1/CC2, control signals, and GND.

J2-J11 are DNP in the core single-sided SMT build. The control/diagnostic headers, terminal blocks, and breadboard headers therefore require a secondary through-hole assembly operation. Qualify SMT connector alternatives if the final product must have zero manual assembly.

Do not route 2-3 A through a solderless breadboard or Dupont jumper. Use the terminal blocks and appropriately sized wire for load and thermal testing.

Design authorities#

• TI TPS25730A data sheet
• TI TPSM63603 data sheet
• TI TVS2200 data sheet
• GCT USB4105 mechanical drawing
• GCT USB4105 product specification
• Panasonic 25SVPF47M OS-CON series

Release gates#

• [x] Freeze 15 V / 3 A input contract and four 3 A output targets.
• [x] Select a firmware-free PD3.2 controller with protected sink path.
• [x] Select a 36 V-tolerant integrated-inductor regulator family.
• [x] Calculate feedback, frequency, minimum effective capacitance, and input power budget.
• [x] Complete schematic capture and pass ERC with zero errors and warnings.
• [x] Independently verify the custom TPSM63603 RDH0030A land pattern against the TI package drawing.
• [x] Complete four-layer placement/routing and pass DRC, connectivity, and schematic-parity checks.
• [x] Analytically validate strap corners, feedback values, capacitance windows, power budget, copper drop, and preliminary thermal behavior.
• [x] Run averaged ngspice protected-bus startup, combined-load, and source-mismatch scenarios.
• [ ] Archive exact vendor DC-bias curves for the production capacitor lots; the 1.1 V and 1.8 V output banks have the narrowest worst-corner margin.
• [ ] Assemble prototypes and complete the documented bench matrix.
• [x] Generate and inspect Gerbers, drills, BOM, pick-and-place, schematic PDF, assembly PDF, SVG preview, checksums, and fabrication ZIP.
• [ ] Complete USB-IF/EMC/safety/environmental work required for any external certification claim.

Local commands#

# Schematic and local libraries
python3 boards/usb-c-multi-rail-power/generate_design.py

# PCB: use KiCad's bundled Python so pcbnew matches KiCad
/Applications/KiCad/KiCad.app/Contents/Frameworks/Python.framework/Versions/Current/bin/python3 \
  boards/usb-c-multi-rail-power/generate_pcb.py

# Fabrication/assembly package, then full QA + HTML report
python3 boards/usb-c-multi-rail-power/manufacturing/generate_outputs.py
python3 boards/usb-c-multi-rail-power/qa/run_preflight.py

The PCB generator refuses to overwrite the production file while a KiCad project lock exists. Close the board before intentionally regenerating it; do not use --force over an active editor session.