I/O modules

AXO-001 — LED bar + traffic light PMOD module

Catalog #1 in the AruviX output line, level L1 (GPIO). The first-blinky board: the module a student plugs in before anything else.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 BAR0 BAR0_A BAR1 BAR1_A BAR2 BAR2_A BAR3 BAR3_A BAR4 BAR4_A BAR5 BAR5_A BAR6 BAR6_A BAR7 BAR7_A GND TRAF_G_A TRAF_R_A TRAF_Y_A

Production status#

Source: boards/io-modules/axo-001-led-bar

Catalog #1 in the AruviX output line (../README.md), level L1 (GPIO). The first-blinky board: the module a student plugs in before anything else.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Driving outputs at all: first blinky, binary up/down counters on the 8-bit bar, PWM dimming, Knight Rider chasers — and a traffic-light state machine, all on one Type 1 PMOD.

Design decision: 8 pins, 11 LEDs, two lessons#

• The bar is 8 discrete 0603 green LEDs (Kingbright APT1608SGC), not a 10-segment bar-graph package: discrete 0603s use a stock KiCad footprint, are cheaper, and an 8-bit bar matches an 8-pin PMOD byte exactly.
• The 3 traffic LEDs — red APT1608SURCK, yellow APT1608SYCK, green APT1608SGC — are wired in parallel with bar segments 0-2, each through its own 330 Ω ballast resistor. PMOD pins 1-3 therefore drive the traffic head AND the bar LSBs at the same time. That sharing is documented on the schematic and is itself the lesson: one net, two loads, independent ballast so brightness stays per-LED.
• Every line is host-driven: pin → 330 Ω → LED → GND (~3–5 mA per LED at 3.3 V; ≤ 2 LEDs per pin, well within an ECP5 I/O). No module-driven lines, so the sensor line's 100 Ω series-resistor rule does not apply beyond the ballast resistors.
• 11 LEDs + 11 resistors total; no ICs, so no decoupling required.

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout (traffic head grouped and silkscreened R/Y/G), DRC, fab outputs
• [ ] hdl/: blinky, counter, PWM dimmer, chaser, traffic-light FSM demos
• [ ] BOM export and availability check, design-review checklist