Sensor modules

AXS-050 — OV7670 camera carrier dual-PMOD module (flagship)

Catalog #50 in the AruviX sensor line, level L5 (parallel DVP capture + SCCB configuration).

Level L5 ERC clean No layout No fab package 20 components

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	Socket decoupling	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	10uF 10V X5R	Sensor core/analog bulk reservoir at the socket	`GRM21BR61A106KE19L` Murata	`C_0805_2012Metric`
`J1`	PMOD A: DATA	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J2`	OV7670 SOCKET (2x9)	Socket for the common 18-pin OV7670 breakout (no FIFO)	not selected generic	`PinSocket_2x09_P2.54mm_Vertical`
`J3`	PMOD B: CTRL	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`R1`	100R	Series protection on the camera-driven D0 line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	100R	Series protection on the camera-driven D1 line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R3`	100R	Series protection on the camera-driven D2 line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R4`	100R	Series protection on the camera-driven D3 line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R5`	100R	Series protection on the camera-driven D4 line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R6`	100R	Series protection on the camera-driven D5 line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R7`	100R	Series protection on the camera-driven D6 line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R8`	100R	Series protection on the camera-driven D7 line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R9`	100R	Series protection on the camera-driven pixel clock line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R10`	100R	Series protection on the camera-driven line valid line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R11`	100R	Series protection on the camera-driven frame sync line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R12`	4.7k	SCCB clock pull-up (SCCB is I2C-compatible; no jumper - bus is dedicated)	`RC0603FR-074K7L` Yageo Datasheet ↗	`R_0603_1608Metric`
`R13`	4.7k	SCCB data pull-up	`RC0603FR-074K7L` Yageo Datasheet ↗	`R_0603_1608Metric`
`R14`	10k	RESET_N pull-up: camera out of reset until the host drives it low	`RC0603FR-0710KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R15`	10k	PWDN pull-down: camera powered up until the host drives PWDN high	`RC0603FR-0710KL` Yageo Datasheet ↗	`R_0603_1608Metric`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 CAM_D0 CAM_D1 CAM_D2 CAM_D3 CAM_D4 CAM_D5 CAM_D6 CAM_D7 CAM_HREF CAM_PCLK CAM_VSYNC D0 D1 D2 D3 D4 D5 D6 D7 GND HREF PCLK PWDN RESET_N SIOC SIOD VSYNC XCLK

Production status#

Schematic ERC	0 violations
PCB layout	not started
DRC	not run
Fab package	not exported
Fabricated	no — design stage only

Source: boards/sensor-modules/axs-050-camera

Catalog #50 in the AruviX sensor line (../README.md), level L5 (parallel DVP capture + SCCB configuration).

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Live video into the FPGA — the capstone of the sensor line. Generate a 24 MHz XCLK from a fabric PLL, configure the sensor over SCCB, then capture the parallel DVP stream: sample D0–D7 on PCLK edges while HREF is high, framed by VSYNC, into a line buffer / framebuffer. Clock-domain crossing, BRAM streaming, and timing constraints all show up here for real.

Dual-PMOD requirement#

This module has two PMOD plugs and needs two adjacent sockets on the ECP5 host (matching the host board's paired-PMOD spacing):

J1 (PMOD A) — 8-bit pixel data D0–D7.
J3 (PMOD B) — PCLK, XCLK, HREF, VSYNC, SCCB (SIOC/SIOD), RESET_N, PWDN.

J1 pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	D0	D1	D2	D3	GND	3V3	D4	D5	D6	D7	GND	3V3

J3 pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	PCLK	XCLK	HREF	VSYNC	GND	3V3	SIOC	SIOD	RESET_N	PWDN	GND	3V3

Camera socket (J2)#

A stock 2×9 pin socket (Connector_PinSocket_2.54mm:PinSocket_2x09_P2.54mm_Vertical) for the common 18-pin no-FIFO OV7670 breakout. The KiCad odd/even numbering matches the common breakout's own numbering:

Odd (left)	1 3V3	3 SIOC	5 VSYNC	7 PCLK	9 D7	11 D5	13 D3	15 D1	17 RESET
Even (right)	2 GND	4 SIOD	6 HREF	8 XCLK	10 D6	12 D4	14 D2	16 D0	18 PWDN

Order-check warning: 18-pin OV7670 breakouts are mostly-but-not-always identical. Verify your board's silkscreen against this table before fitting.

Design#

All camera-driven lines pass 100 Ω series: D0–D7 (R1–R8), PCLK (R9), HREF (R10), VSYNC (R11). XCLK is host-driven, wired directly.
SCCB is I2C-compatible (7-bit address 0x21, 100 kHz): SIOC/SIOD get fixed 4.7 k pull-ups (no solder jumpers — the bus is dedicated to this camera, never chained).
RESET_N: 10 k pull-up (camera runs by default); PWDN: 10 k pull-down (camera powered by default). Both host-controllable on J3 pins 9/10.
100 nF + 10 µF at the camera socket.
XCLK = 24 MHz from a fabric PLL; PCLK returns at up to 24 MHz — treat it as a real clock (dedicated input routing, its own clock domain).

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout: plug spacing must match the ECP5 host's adjacent PMOD sockets exactly; length-match the D bus loosely; PCLK away from XCLK
[ ] Verify OV7670 breakout pinout against a purchased board
[ ] hdl/: SCCB master, capture front-end (PCLK domain), line buffer + CDC FIFO, test-pattern check, testbench, ECP5 demo
[ ] BOM export and availability check, design-review checklist