← usb-c-multi-rail-power

Circuit review & bench-test guide

USB-C multi-rail power module

Document purpose#

This guide explains the usb-c-multi-rail-power prototype and provides a repeatable manual-review, first-power-up, and bench-validation procedure. It is derived from the implemented schematic/PCB, frozen BOM, design values, architecture contract, simulation, and QA evidence in this directory.

The repository records 28 PASS, 5 CONDITIONAL, 7 OPEN, and 0 FAIL preflight results. No assembled-board evidence closes the electrical, thermal, interoperability, fault, sequencing, or certification gates. Treat all calculated values as hypotheses to measure.

1. What the board does#

The board negotiates exactly 15 V at 3 A from a suitable USB-C PD source. A TPS25730AD PD controller contains the protected sink switch and deliberately keeps its PD_15V output off if the source cannot satisfy the configured voltage/current capability. Four independent TPSM63603 synchronous buck power modules then generate simultaneous 3 A rails:

• 1.1 V at 3 A;
• 1.8 V at 3 A;
• 3.3 V at 3 A; and
• 5.0 V at 3 A.

There is no reduced-power 5 V/9 V/12 V fallback. All four buck channels default on once the protected 15 V bus is available. Their EN and PG signals are exposed, but the board does not implement a sequencer, per-rail crowbar, or secondary output overvoltage protection.

Functional block diagram#

                           CC1 / CC2
USB-C J1 ──────────────────────┐
                              v
VBUS_RAW ───────────────> TPS25730AD U1
   │                      PD negotiation + protected sink path
   ├── D1 TVS2200                 │
   ├── D2 negative clamp          │ only for valid 15 V / 3 A contract
   ├── C1 + C32-C35               v
   └── CC filters C2/C3        PD_15V bus
                                  │
             ┌────────────────────┼────────────────────┐
             v                    v                    v
       TPSM63603 U2         TPSM63603 U3          TPSM63603 U4/U5
        1.1 V / 3 A          1.8 V / 3 A          3.3 V and 5 V / 3 A
             │                    │                    │
        J4 / J5              J6 / J7              J8-J11 outputs

2. Safety and operating boundaries#

• Use only a certified isolated USB-PD source or a current-limited PD emulator.
• Simultaneous full load is 33.6 W output and about 40 W estimated input. Use the Phoenix terminals, appropriate wire, fusing/test fixtures, and electronic loads. Keep each breadboard header at or below 0.5 A.
• Connect earth-referenced scope ground only to board GND. Use spring-ground or coax/differential probing for ripple; long probe leads produce false spikes.
• Never externally drive an output above nominal. Prebiased startup is supported by the modules, but system-level reverse-energy behavior remains an open test.
• The four rails start together by default. A downstream FPGA or ASIC may need rail sequencing, supervisor, and independent OVP that this generic board does not provide.
• Do not substitute a generic 5.5 V clamp on CC1/CC2. The correct protection must tolerate the USB-C CC short-to-VBUS fault environment.
• IEC ESD/surge and EMC work require controlled laboratory equipment. This board has not earned USB-IF, EMC, safety, or environmental certification.

3. Startup and power flow#

1. Before attachment, U1 is in its VBUS-powered/dead-battery configuration. VIN_3V3 is grounded as prescribed for this standalone mode.
2. A source detects the sink through CC1 or CC2 and applies initial VBUS.
3. U1's internal VBUS LDO generates PD_LDO_3V3; C5 and C6 stabilize its 3.3 V and 1.5 V internal rails.
4. U1 samples ADCIN1–ADCIN4. The dividers encode minimum 15 V, maximum 15 V, operating 3 A, maximum 3 A. PD5VMAX is strapped low.
5. If the source does not offer 15 V/3 A, U1 asserts capability mismatch and keeps the sink path off. There is intentionally no converter input.
6. After a valid explicit contract, U1's integrated protected high-voltage path slews PD_15V up while providing overvoltage and reverse-current protection.
7. C7 and all eight converter input MLCCs charge. The four EN pull-ups then allow U2–U5 to start.
8. Each module switches at its programmed frequency, regulates from a 1.0 V feedback reference, and releases its open-drain PG output when valid.

Contract strap truth#

All values are 1% E96. An incorrect divider can change the requested contract or mismatch policy, so verify installed values before applying expensive loads.

4. External interfaces and test points#

Connectors#

Core SMT manufacture leaves J2–J11 unpopulated. Manual/secondary assembly is therefore required before ordinary output testing.

Test points#

J2 pinout is: 1=3V3, 2=GND, 3=PD_FAULT_N, 4=CAP_MIS_N, 5/6=EN/PG 1.1 V, 7/8=EN/PG 1.8 V, 9/10=EN/PG 3.3 V, and 11/12=EN/PG 5.0 V. EN may be pulled low externally; never drive it above the local 3.3 V logic rail. PG is open-drain with a 47 kΩ local pull-up.

5. Component-by-component circuit review#

5.1 USB-C and PD protected input#

U1 tolerates/monitors higher CC fault voltages, but no dedicated external IEC ESD/short-to-VBUS protector is fitted. That remains an explicit pre-compliance decision, not an oversight to fix with an arbitrary low-voltage TVS.

5.2 PD controller support and diagnostics#

5.3 Four TPSM63603 converter channels#

U2–U5 are TI TPSM63603RDHR modules. Each integrates controller, MOSFETs, and inductor, operates from 3–36 V, and delivers up to 3 A. The module needs external input/output capacitors, feedback, frequency programming, EN/PG bias, and correct thermal land/vias.

The custom 4×6 mm RDH0030A footprint follows TI's assembled EVM geometry. Four thermal vias under each module must be filled/planarized from the component side. Missing fill can wick solder, create voids, tilt the module, and increase thermal resistance. X-ray inspection is strongly recommended.

5.4 Output capacitors and connectors#

MLCC nameplate capacitance is not effective capacitance. DC bias, tolerance, temperature, aging, and lot/part substitution must be included. Do not replace these capacitors merely by matching the printed µF value.

6. Datasheet summary and design interpretation#

Official references: TPS25730A datasheet/product, TPSM63603 datasheet/product, TVS2200 datasheet/product, Murata GRM31CR71H475KA12L sheet, and Panasonic 25SVPF47M. Use the current revision and exact orderable suffix at purchase time.

7. Calculated targets and margins#

Output and input power#

Capacitance evidence gates#

Regulation and thermal screening#

The temperature estimates use 33.5 °C/W and exclude mutual heating, enclosure, airflow, copper/process variation, and ambient rise. The 5 V channel is the first thermal focus. Resistor-only voltage ranges also exclude module reference, load regulation, ripple, DMM error, and PCB drop.

8. Manual review checklist#

• Confirm J1 CC1/CC2 separation and every VBUS/GND contact. Inspect shell stakes and connector coplanarity/retention.
• Verify exact U1 and U2–U5 suffixes, orientation, exposed-pad solder, and thermal-via fill/planarity. X-ray all five power QFNs/modules if possible.
• Verify D1/D2 and polarized C7 orientation.
• Measure R1–R10 strap values in-circuit or before U1 population; compare divider ratios with the table.
• Confirm C7 plus all eight module input MLCCs are the exact approved MPNs.
• Normalize conservative value-field voltage labels versus frozen Murata MPN ratings so schematic, BOM, incoming inspection, and purchase order agree.
• Verify each feedback pair, RT resistor, and output capacitor bank by channel; swapping the 1.1 V and 5 V feedback networks can destroy a load.
• Confirm J2–J11 DNP/population state matches the planned assembly variant.
• Check continuity and isolation between all four outputs. No output should be shorted to another rail or to the 15 V bus.
• Inspect the 5 mm In2 bus spine, branch vias, output planes, and terminal solder for voids, neck-down damage, and unintended copper exposure.

9. Ordered bench-test procedure#

Stop on the first unexpected result. Record board serial/revision, assembly variant, source/cable, equipment and calibration, ambient, raw waveform files, photos, operator, and disposition.

A. Unpowered checks#

1. With USB and loads disconnected, inspect and complete the checklist above.
2. Measure VBUS_RAW-to-GND, PD_15V-to-GND, and every output-to-GND resistance in both meter polarities. Investigate a hard short.
3. Check rail-to-rail isolation and terminal polarity.
4. Verify ADC divider values and that EN defaults high through 100 kΩ while PG has 47 kΩ pull-up paths.

B. PD contract and protected path, no converter loads#

1. Use a PD analyzer/emulator capable of controlled advertised PDOs. Start with a 15 V/3 A-capable source and no external rail load.
2. Attach in both cable orientations. Confirm the explicit 15 V/3 A contract, TP1 raw VBUS, TP2 protected-bus slew, CAP_MIS_N, PD_FAULT_N, and SINK_EN_N.
3. Repeat with sources offering only 5 V, 9 V, 12 V, 15 V below 3 A, and an adequate 15 V/3 A source. In every mismatch case, TP2 must remain off.
4. Repeat across at least three independent ≥45 W adapters and representative cables. Record attach time, retries, resets, and bus overshoot.

C. First rail power-up#

1. Power from a valid source with no external load. Observe all four rails, EN, and PG simultaneously if possible.
2. Confirm monotonic startup, no output exceeding its limit, and no unexpected rail-to-rail ordering claim. Record actual timing.
3. Measure rail DC voltage at both the test point and populated terminal. Use the resistor-only ranges as a review aid, not final acceptance limits.
4. Pull each EN low individually through J2/test fixture; confirm only the corresponding rail turns off and its PG deasserts. Never drive EN high from an external 5 V source.

D. Individual load sweeps and dynamics#

1. For each rail use its full-load terminal, short heavy leads, remote DMM sense at the terminal, and a suitable electronic load.
2. Sweep 0, 0.1, 0.5, 1, 2, and 3 A while other rails are unloaded. Record DC voltage, input current, module/terminal/capacitor temperature, and PG.
3. Apply 10%↔100% load steps. Capture undershoot, overshoot, settling, PG, and input-bus movement with probe bandwidth explicitly recorded.
4. Measure ripple using a spring ground or coax at the terminal/capacitor.

E. Combined load and thermal soak#

1. Increase all rails in stages while monitoring total input. Confirm the PD contract remains stable and TP2 does not collapse.
2. Run each channel at 3 A, then all four together at 3 A for 60 minutes at room and worst intended ambient.
3. Log U1, U2–U5, J1, C7, output capacitors, terminals, and bus/plane hot spots. Compare especially U5 against the preliminary +69 °C rise estimate.
4. Stop before exceeding component junction/case, PCB, connector, wire, or enclosure limits. Case temperature is not junction temperature.

F. Fault, prebias, and reverse-energy tests#

1. Using a protected fixture, current-limit/short each rail individually and then test planned simultaneous-fault cases. Capture current, VOUT, PG, module temperature, PD bus, and recovery mode.
2. Test hot-plug with zero load and maximum permitted preload.
3. With USB absent, apply a controlled prebias below nominal to one output and then attach USB. Verify monotonic startup and reverse current.
4. Perform current-limited reverse injection only under a written limit plan. Confirm other rails and PD_15V do not rise dangerously.
5. A module surviving one short does not validate repeated fault energy or enclosure safety; cool and inspect between tests.

G. Release-only testing#

Complete USB interoperability, CC short-to-VBUS/IEC protection decision, ESD, surge, conducted/radiated EMC, product safety, FPGA-specific sequencing/OVP, and production environmental compliance in suitable labs. The bare module's successful bench test is not a compliance certificate.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The board has a clear fail-closed input policy: its converter tree should see power only after an explicit 15 V/3 A contract. The four-module topology is straightforward and independently controllable, but the simultaneous 33.6 W load leaves limited source and thermal margin. The highest-priority closures are actual PD source/cable rejection behavior, exact capacitance retention, full-load regulation/dynamics, module and connector thermal soak, fault and reverse-energy behavior, CC protection strategy, and any downstream system's sequencing/OVP requirements.