Sensor modules

AXS-007 — SHT31 temperature/humidity PMOD module

Catalog #7 in the AruviX sensor line, level L3 (I2C protocol FSM). First pilot module; also the proving ground for the shared generator.

Level L3 ERC clean DRC clean Fab package 11 components

3D render of the AXS-007 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	Sensor decoupling at U1 VDD	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	1uF 10V X7R	Module bulk decoupling at the PMOD plug	`GRM188R71A105KA61D` Murata	`C_0603_1608Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`JP1`	SDA PULL-UP	Cut to remove the SDA pull-up when chaining modules	—	`SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`
`JP2`	SCL PULL-UP	Cut to remove the SCL pull-up when chaining modules	—	`SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`
`JP3`	ADDR 0x44/0x45	I2C address select: 1-2 ADDR low 0x44 (default), 2-3 ADDR high 0x45	—	`SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm`
`R1`	4.7k	I2C SDA pull-up	`RC0603FR-074K7L` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	4.7k	I2C SCL pull-up	`RC0603FR-074K7L` Yageo Datasheet ↗	`R_0603_1608Metric`
`R3`	10k	~RESET idle pull-up so an unconfigured host FPGA pin cannot float the sensor into reset	`RC0603FR-0710KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R4`	100R	Series protection on the sensor-driven ALERT line (miswire tolerance per line design rules)	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`U1`	SHT31-DIS-B	Digital temperature and relative-humidity sensor, +/-0.2C +/-2%RH	`SHT31-DIS-B2.5KS` Sensirion Datasheet ↗	`Sensirion_DFN-8-1EP_2.5x2.5mm_P0.5mm_EP1.1x1.7mm`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 ADDR ALERT GND RESET_N SCL SCL_PU SDA SDA_PU SHT_ALERT

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/sensor-modules/axs-007-sht31

Catalog #7 in the AruviX sensor line (../README.md), level L3 (I2C protocol FSM). First pilot module; also the proving ground for the shared generator in ../common/sensor_module_lib.py.

Status: schematic ERC clean (0/0), netlist reviewed; PCB layout complete — DRC 0 electrical / 0 unconnected / 0 parity (one waived lib_footprint_mismatch from moving J1's overhanging silk to F.Fab, same precedent as usb-c-5v-breakout U2). Renders in reports/review/. Not released.

What it teaches#

Writing an I2C master in Verilog: start/stop conditions, clock stretching, 16-bit commands, CRC-8 checking of the sensor's measurement frames, and an ALERT interrupt line for threshold-crossing events.

Design#

Sensor: Sensirion SHT31-DIS-B (±0.2 °C, ±2 %RH), DFN-8.
Interface: PMOD Type 6 (I2C) on the top row, bus repeated on the bottom row for daisy-chain experiments:

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	ALERT	~RESET	SCL	SDA	GND	3V3	NC	NC	SCL	SDA	GND	3V3

I2C address: 0x44 with JP3 in the default 1-2 position (ADDR low); bridge 2-3 instead for 0x45 so two modules can share a bus.
Pull-ups: 4.7 kΩ on SCL/SDA through solder jumpers JP1/JP2, fitted by default. Cut them when another module on the chain provides the pull-ups.
~RESET: 10 kΩ pull-up so an unconfigured FPGA pin cannot hold the sensor in reset.
ALERT: 100 Ω series resistor (sensor-driven line, per the line-wide miswire-tolerance rule).
The 2×6 header zigzag numbering vs. PMOD row numbering is translated in the generator (PMOD_TO_HEADER in the common library); layout must place header pin 1 at the PMOD pin-1 position — verify against a host socket before release.

Regenerate#

python3 generate_design.py   # emits .kicad_sch and .kicad_pro

reports/erc.rpt is the last kicad-cli ERC run.

Regenerate the PCB#

/Applications/KiCad/KiCad.app/Contents/Frameworks/Python.framework/Versions/Current/bin/python3 generate_pcb.py

Remaining for release#

[x] PMOD pin-1 orientation verified against Digilent spec 1.2.0 Figure 2 (pin 1 top-right, pins 1-6 upper row — matches this layout; see ../../pmod-common/PMOD-SPEC-NOTES.md). Host-socket cross-check remains part of ECP5 rev-A review.
[ ] Fab outputs (gerbers/drill/position) and a release-QA run
[ ] hdl/: I2C master core, SHT31 controller, self-checking testbench, ECP5 demo top (Yosys → nextpnr-ecp5 → ecppack)
[ ] BOM export and part-availability check
[ ] Design-review checklist