Actuator modules

AXA-008 — ULN2003A low-side driver pack PMOD module

Catalog #8 in the AruviX actuator line, level L1. Four open-collector Darlington channels for solenoids, relays, pumps, and vibration motors — the cheapest useful module in the line.

Level L1 ERC clean DRC clean Fab package 5 components

3D render of the AXA-008 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 50V X7R	VLOAD-GND decoupling at the array: snubs the clamp-diode recovery edge	`GRM188R71H104KA93D` Murata	`C_0603_1608Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J3`	VLOAD IN (MAX 24V)	Load supply input: 1 VLOAD (up to 24 V), 2 GND (joins PMOD GND here)	not selected Phoenix Contact	`TerminalBlock_Phoenix_MKDS-1,5-2-5.08_1x02_P5.08mm_Horizontal`
`J4`	OUT1-OUT4	Low-side outputs: load wires from VLOAD to OUTx; channel sinks to GND	not selected Phoenix Contact	`TerminalBlock_Phoenix_MKDS-1,5-4-5.08_1x04_P5.08mm_Horizontal`
`U1`	ULN2003A	7-channel Darlington sink driver with internal clamp diodes	`ULN2003ADR` Texas Instruments Datasheet ↗	`SOIC-16_3.9x9.9mm_P1.27mm`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 CH1 CH2 CH3 CH4 GND OUT1 OUT2 OUT3 OUT4 VLOAD

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/actuator-modules/axa-008-lowside

Catalog #8 in the AruviX actuator line (../README.md), level L1. Four open-collector Darlington channels for solenoids, relays, pumps, and vibration motors — the cheapest useful module in the line.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

GPIO load switching and flyback. An inductive load stores energy in its magnetic field; at turn-off the coil current cannot stop instantly, so the collapsing field drives the output pin voltage above the supply until something conducts (kickback). The ULN2003A's COM pin ties to VLOAD, so its internal clamp diodes freewheel that current back into the supply instead of letting it avalanche the Darlingtons — watch the turn-off edge on a scope with and without a relay coil to see why every driven output in this line needs a flyback path.

Design#

ULN2003ADR (TI), SOIC-16. Internal ~2.7 kΩ base resistors let the host's 3.3 V GPIO drive inputs 1–4 directly from PMOD pins 1–4 — no external parts on the signal path (all lines host-driven, no series resistors per the line rule).
Load power (VLOAD, up to 24 V) enters on the J3 screw terminal only — never through the PMOD. Grounds join on the module.
Each channel sinks up to ~500 mA (derate for multiple simultaneous channels; parallel channels for more). Loads wire from VLOAD to an OUTx terminal on J4 (MKDS 1x04); the channel pulls the low side to GND.
COM → VLOAD: the built-in flyback/freewheel path (line flyback rule).
Unused inputs 5–7 are tied to GND (spare Darlingtons hard off); unused outputs 5–7 are left open (no-connect).
100 nF VLOAD–GND at the array — the array's "supply" is the load rail via COM, so that is where the decoupling goes (50 V-rated part for 24 V rails).

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	CH1	CH2	CH3	CH4	GND	3V3	NC	NC	NC	NC	GND	3V3

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (20 × 40 mm actuator outline), DRC, fab outputs
[ ] hdl/: GPIO/PWM channel driver demo (relay click, pump PWM), testbench
[ ] BOM export and availability check, design-review checklist