Lab modules

AXL-001 — 8-channel logic analyzer pod PMOD module

Catalog #1 in the AruviX lab line, level L3 (instrument). The FPGA becomes the test equipment: this pod feeds 8 buffered probe inputs into a capture core students write themselves.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 CH0 CH0_BUF CH0_IN CH1 CH1_BUF CH1_IN CH2 CH2_BUF CH2_IN CH3 CH3_BUF CH3_IN CH4 CH4_BUF CH4_IN CH5 CH5_BUF CH5_IN CH6 CH6_BUF CH6_IN CH7 CH7_BUF CH7_IN GND PROBE0 PROBE1 PROBE2 PROBE3 PROBE4 PROBE5 PROBE6 PROBE7

Production status#

Source: boards/lab-modules/axl-001-la-pod

Catalog #1 in the AruviX lab line (../README.md), level L3 (instrument). The FPGA becomes the test equipment: this pod feeds 8 buffered probe inputs into a capture core students write themselves.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Trigger FSMs, BRAM ring buffers, run-length encoding, and a real host protocol: the companion la_capture core captures to BRAM and sump_uart speaks the sigrok/SUMP protocol so PulseView connects directly over the UART. After this lab the pod is the platform's debug workhorse forever.

Design#

• SN74LVC245APW buffer at VCC = 3.3 V. LVC inputs are 5 V-tolerant at 3.3 V supply — the deciding factor (per the line README review findings): the pod must survive probing 5 V DUTs.
• DIR hardwired low (B→A: probes enter the B port, PMOD leaves the A port), ~OE hardwired low (always enabled).
• Per channel: 100 kΩ pull-down (defined idle level for floating probes) → 1 kΩ series (fault-current limit from hot/miswired DUTs) → buffer → 100 Ω series → PMOD (module-driven line rule).
• Probe header J2: 2x05 vertical pin header, pins 1–8 = CH0–CH7 tips, pins 9/10 = probe grounds. MPN TBD (shrouded preferred for keyed pods).

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout, DRC, fab outputs
• [ ] hdl/: la_capture + sump_uart instantiation, testbench, ECP5 demo
• [ ] Pin the probe-header MPN; ship PulseView config + prebuilt bitstream
• [ ] BOM export and availability check, design-review checklist