Sensor modules

AXS-006 — DS18B20 1-Wire temperature PMOD module

Catalog #6 in the AruviX sensor line, level L2 (microsecond pulse timing on a single open-drain wire).

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 GND OW

Production status#

Source: boards/sensor-modules/axs-006-ds18b20

Catalog #6 in the AruviX sensor line (../README.md), level L2 (microsecond pulse timing on a single open-drain wire).

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

The 1-Wire protocol is pure timing: 480 µs reset pulses, presence detection, 60 µs bit slots, and 64-bit ROM addressing — an ideal FPGA counter/FSM exercise with no protocol hardware to lean on. With a second sensor on J2 the lesson extends to multi-drop ROM search.

Design#

• Onboard DS18B20U (µSOP-8), VDD wired (parasite power not used).
• 4.7 kΩ pull-up on the bus; no series resistor on DQ — the line is open-drain and the pull-up already limits fault current, so a series element would only degrade the shared bus edges.
• J2 (DNP, 1×3: 3V3 / OW / GND) accepts a second DS18B20 or a waterproof probe on the same bus.
• The host must drive OW only as open-drain: output 0 or release to input.

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout (20 × 25 mm outline), DRC, fab outputs
• [ ] hdl/: 1-Wire master core, testbench, ECP5 demo
• [ ] BOM export and availability check, design-review checklist