Lab modules

AXL-002 — Oscilloscope front end dual-PMOD module (AD9280)

Catalog #2 in the AruviX lab line, level L5 (instrument). Dual-PMOD module (binding review finding): 8 data bits + the ADC clock exceed one socket's 8 IO — same host constraint as axs-050/axo-007, plugs on 0.9" centers, and CLK needs the clock-capable host pin tracked.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 ADC_D0 ADC_D1 ADC_D2 ADC_D3 ADC_D4 ADC_D5 ADC_D6 ADC_D7 ADC_OTR AIN AVDD_F CLK D0 D1 D2 D3 D4 D5 D6 D7 GND OTR REFBF REFSENSE REFTF REF_DIV SIG_IN STBY STBY_S VIN VREF

Production status#

Source: boards/lab-modules/axl-002-scope

Catalog #2 in the AruviX lab line (../README.md), level L5 (instrument). Dual-PMOD module (binding review finding): 8 data bits + the ADC clock exceed one socket's 8 IO — same host constraint as axs-050/axo-007, plugs on 0.9" centers, and CLK needs the clock-capable host pin tracked in boards/BACKLOG.md.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Triggering, decimation, pre-trigger ring buffers (scope_capture core) — then plot on the VGA module (axo-007) for a fully standalone scope. Pairs with AXL-003 as its own test source.

Design#

• AD9280ARSZ, 8-bit 32 MSPS parallel ADC. The stock symbol has no default footprint — Package_SO:SSOP-28_5.3x10.2mm_P0.65mm is assigned explicitly (per the line README footprint sweep).
• Reference topology (state loudly): MODE = AVDD → top/bottom reference mode; REFTS = VREF, REFBS = AVSS → input span 0 V..VREF. Internal reference: JP4 default (1-2) puts REFSENSE on the R3/R4 tap, VREF = 1.25 V × (1 + 6.2k/10k) ≈ 2.02 V — the datasheet single-supply 0–2 V configuration. JP4 2-3 gives REFSENSE = VREF → VREF = 1.25 V. REFTF/REFBF carry the datasheet decoupling (100 nF each + 10 µF across).
• Front end, rev-1 DC-coupled low-voltage only (deferred note): 1×02 header in parallel with a BNC (BNC_Amphenol_B6252HB-NPP3G-50_Horizontal — stock footprint verified, so the BNC is fitted). JP3 bridged (default) = 1:1, 0–2 V, 100k input impedance; cut JP3 = 10.1:1 divider (910k/100k — 910k is the closest E24 value to 900k), ≈0–20 V. BAT54S clamps the buffer input to the rails. No AC coupling, no offset, no negative range — silkscreen warning required.
• OPA356AIDR rail-to-rail unity buffer drives AIN (DC-coupled; with the 0–2 V span, mid-scale = 1 V comes from the signal itself in rev 1).
• AVDD filter: no stock-verified ferrite bead in the platform BOM, so AVDD = 3V3 through 10 Ω + 10 µF/100 nF (documented substitution). DRVDD ties to 3V3 directly.
• STBY: 10 kΩ pull-down strap = run by default; host may drive it via J3-3. THREE-STATE, CLAMP, CLAMPIN tied low. All ADC-driven lines (D0–D7, OTR) pass 100 Ω series.
• Sample rate: 25 MHz from the host fabric (part rated 32 MSPS).

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout (dual plugs on 0.9" centers), DRC, fab outputs
• [ ] Silkscreen warning: DC-coupled, 0–2 V (0–20 V at 10:1), no isolation
• [ ] hdl/: scope_capture core, testbench, ECP5 + VGA demo
• [ ] BOM export and availability check, design-review checklist