I/O modules
AXO-003 — Shift-register lab PMOD module
Catalog #3 in the AruviX output line, level L2 (serial shift — roll your own SPI). Two cascaded 74HC595 shift registers: the first drives a single-digit 7-segment display, the second drives 8 discrete LEDs. The QH' → SER cascade is the lesson: after bit-banging this chain the student has independently invented SPI daisy-chaining.
Circuit review & bench-test guide →
Components#
Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.
| Ref | Value | What it does on this board | Part number | Footprint |
|---|---|---|---|---|
C1 |
100nF 16V X7R | U1 supply decoupling | GRM188R71C104KA01DMurata |
C_0603_1608Metric |
C2 |
100nF 16V X7R | U2 supply decoupling | GRM188R71C104KA01DMurata |
C_0603_1608Metric |
D1 |
GREEN | LED bank bit 1 (lit = logic 1 in U2 bit QA) | APT1608SGCKingbright Datasheet ↗ |
LED_0603_1608Metric |
D2 |
GREEN | LED bank bit 2 (lit = logic 1 in U2 bit QB) | APT1608SGCKingbright Datasheet ↗ |
LED_0603_1608Metric |
D3 |
GREEN | LED bank bit 3 (lit = logic 1 in U2 bit QC) | APT1608SGCKingbright Datasheet ↗ |
LED_0603_1608Metric |
D4 |
GREEN | LED bank bit 4 (lit = logic 1 in U2 bit QD) | APT1608SGCKingbright Datasheet ↗ |
LED_0603_1608Metric |
D5 |
GREEN | LED bank bit 5 (lit = logic 1 in U2 bit QE) | APT1608SGCKingbright Datasheet ↗ |
LED_0603_1608Metric |
D6 |
GREEN | LED bank bit 6 (lit = logic 1 in U2 bit QF) | APT1608SGCKingbright Datasheet ↗ |
LED_0603_1608Metric |
D7 |
GREEN | LED bank bit 7 (lit = logic 1 in U2 bit QG) | APT1608SGCKingbright Datasheet ↗ |
LED_0603_1608Metric |
D8 |
GREEN | LED bank bit 8 (lit = logic 1 in U2 bit QH) | APT1608SGCKingbright Datasheet ↗ |
LED_0603_1608Metric |
J1 |
PMOD PLUG 2x6 | PMOD peripheral plug (Digilent spec 1.2) | not selected generic |
PinHeader_2x06_P2.54mm_Horizontal |
R1 |
220R | Segment A ballast from U1 QA | RC0603FR-07220RLYageo Datasheet ↗ |
R_0603_1608Metric |
R2 |
220R | Segment B ballast from U1 QB | RC0603FR-07220RLYageo Datasheet ↗ |
R_0603_1608Metric |
R3 |
220R | Segment C ballast from U1 QC | RC0603FR-07220RLYageo Datasheet ↗ |
R_0603_1608Metric |
R4 |
220R | Segment D ballast from U1 QD | RC0603FR-07220RLYageo Datasheet ↗ |
R_0603_1608Metric |
R5 |
220R | Segment E ballast from U1 QE | RC0603FR-07220RLYageo Datasheet ↗ |
R_0603_1608Metric |
R6 |
220R | Segment F ballast from U1 QF | RC0603FR-07220RLYageo Datasheet ↗ |
R_0603_1608Metric |
R7 |
220R | Segment G ballast from U1 QG | RC0603FR-07220RLYageo Datasheet ↗ |
R_0603_1608Metric |
R8 |
220R | Segment DP ballast from U1 QH | RC0603FR-07220RLYageo Datasheet ↗ |
R_0603_1608Metric |
R9 |
330R | LED 1 ballast from U2 QA | RC0603FR-07330RLYageo Datasheet ↗ |
R_0603_1608Metric |
R10 |
330R | LED 2 ballast from U2 QB | RC0603FR-07330RLYageo Datasheet ↗ |
R_0603_1608Metric |
R11 |
330R | LED 3 ballast from U2 QC | RC0603FR-07330RLYageo Datasheet ↗ |
R_0603_1608Metric |
R12 |
330R | LED 4 ballast from U2 QD | RC0603FR-07330RLYageo Datasheet ↗ |
R_0603_1608Metric |
R13 |
330R | LED 5 ballast from U2 QE | RC0603FR-07330RLYageo Datasheet ↗ |
R_0603_1608Metric |
R14 |
330R | LED 6 ballast from U2 QF | RC0603FR-07330RLYageo Datasheet ↗ |
R_0603_1608Metric |
R15 |
330R | LED 7 ballast from U2 QG | RC0603FR-07330RLYageo Datasheet ↗ |
R_0603_1608Metric |
R16 |
330R | LED 8 ballast from U2 QH | RC0603FR-07330RLYageo Datasheet ↗ |
R_0603_1608Metric |
R17 |
10k | ~SRCLR pull-up: shift chain runs even if the host leaves PMOD pin 4 floating | RC0603FR-0710KLYageo Datasheet ↗ |
R_0603_1608Metric |
U1 |
74HC595 | 8-bit serial-in parallel-out shift register with output latch | 74HC595D,118Nexperia Datasheet ↗ |
SOIC-16_3.9x9.9mm_P1.27mm |
U2 |
74HC595 | 8-bit serial-in parallel-out shift register with output latch | 74HC595D,118Nexperia Datasheet ↗ |
SOIC-16_3.9x9.9mm_P1.27mm |
U3 |
KCSC02-105 | Single-digit 0.2in common-cathode 7-segment display, super bright orange | KCSC02-105Kingbright Datasheet ↗ |
KCSC02-105 |
Signals#
Net labels used in the schematic, which are also the names the HDL top level should use.
3V3 CASCADE GND LED1 LED1_A LED2 LED2_A LED3 LED3_A LED4 LED4_A LED5 LED5_A LED6 LED6_A LED7 LED7_A LED8 LED8_A RCLK SEG_A SEG_A_S SEG_B SEG_B_S SEG_C SEG_C_S SEG_D SEG_DP SEG_DP_S SEG_D_S SEG_E SEG_E_S SEG_F SEG_F_S SEG_G SEG_G_S SER SRCLK SRCLR_N
Production status#
| Schematic ERC | 0 violations |
|---|---|
| PCB layout | complete |
| DRC | 0 violations |
| Fab package | exported (24 gerbers + drill + CPL + BOM) |
| Fabricated | no — design stage only |
Source: boards/io-modules/axo-003-shift-lab
Catalog #3 in the AruviX output line (../README.md), level L2 (serial shift — roll your own SPI). Two cascaded 74HC595 shift registers: the first drives a single-digit 7-segment display, the second drives 8 discrete LEDs. The QH' → SER cascade is the lesson: after bit-banging this chain the student has independently invented SPI daisy-chaining.
Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.
What it teaches#
- What SPI is: shift on clock edge (SRCLK), latch on a separate strobe (RCLK), chain devices through the overflow output (QH').
- Bit order made visible: shift 16 bits MSB-first, the first 8 crawl through U1 into U2's LEDs, the last 8 stay in U1's 7-seg digit.
- Hex-to-segment decode (the seg7 decoder from axo-002, minus the scan).
Design#
- 2× 74HC595D,118 (SOIC-16, Nexperia), both ~OE hard-wired low, shared SRCLK/RCLK, shared ~SRCLR with a 10 kΩ pull-up (chain runs even if the host leaves PMOD pin 4 unconfigured; drive low to blank).
- U1 QA..QG → segments A..G, QH → DP, through 220 Ω each (~6 mA/segment at 3.3 V). Display is a Kingbright KCSC02-105 — stock single-digit 0.2" common-cathode symbol and footprint verified (
Display_7Segment: KCSC02-105), so no discrete-LED fallback was needed. Both CC pins to GND. - U2 QA..QH → LED1..LED8, green 0603 (APT1608SGC) + 330 Ω each (~4 mA).
- Everything active-HIGH (common cathode / grounded LED cathodes).
- 100 nF per 74HC595.
| PMOD pin | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Net | SER | SRCLK | RCLK | ~SRCLR | GND | 3V3 | NC | NC | NC | NC | GND | 3V3 |
Regenerate#
python3 generate_design.py
Remaining for release#
- [ ] PCB layout (20 × 25 mm outline), DRC, fab outputs
- [ ]
hdl/: bit-bang shift driver + seg7 decode reuse, testbench, ECP5 demo - [ ] BOM export and availability check, design-review checklist