I/O modules

AXO-008 — ST7735 1.8" SPI TFT carrier PMOD module

Catalog #8 in the AruviX output line, level L4. Socketed carrier for the ubiquitous 1.8" 128×160 ST7735 SPI TFT breakout — same pattern as the sensor line's ultrasonic (axs-021) and GPS (axs-046) carriers, because ST7735 has no stock KiCad assets (documented deferral).

Level L4 ERC clean DRC clean Fab package 8 components

3D render of the AXO-008 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	Socket decoupling	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	10uF 10V X5R	Bulk reservoir for display + backlight at the socket	`GRM21BR61A106KE19L` Murata	`C_0805_2012Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J2`	ST7735 SOCKET (1x8)	Socket for the common 1.8in ST7735 SPI TFT breakout	not selected generic	`PinSocket_1x08_P2.54mm_Vertical`
`JP1`	BL: 3V3 / PWM	Backlight source select: 1-2 (default) always-on 3V3, 2-3 PWM from PMOD 9	—	`SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm`
`R1`	10k	~RESET pull-up: display out of reset until the host drives it low	`RC0603FR-0710KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	10k	~CS idle pull-up so an unconfigured host cannot clock in garbage	`RC0603FR-0710KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R3`	100R	Backlight LED series resistor (~20 mA into the breakout's LED pin)	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 BL_PWM BL_SRC GND LED_PIN MOSI SCK TFT_CS TFT_DC TFT_RST

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/io-modules/axo-008-tft

Catalog #8 in the AruviX output line (../README.md), level L4. Socketed carrier for the ubiquitous 1.8" 128×160 ST7735 SPI TFT breakout — same pattern as the sensor line's ultrasonic (axs-021) and GPS (axs-046) carriers, because ST7735 has no stock KiCad assets (documented deferral in ../README.md).

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

A write-only SPI display: init-command sequences, DC (data/command) framing, RGB565 pixel pushing at up to ~15 MHz SCK — the FPGA draws with no framebuffer chip in the way. Terminal, gauges, sprite demos.

Design#

J2 = 1×08 pin socket in the most common breakout order: 1 VCC 2 GND 3 CS 4 RESET 5 A0/DC 6 SDA 7 SCK 8 LED. ORDER-CHECK WARNING (on the schematic too): 1.8" clones vary — some swap VCC/GND or move LED. Verify your breakout's silkscreen against this map before soldering the socket or plugging in.
No MISO: the breakout does not bring out the ST7735 read path, so PMOD pin 3 is NC and there are no module-driven lines (the sensor-line 100 Ω rule has nothing to apply to; the backlight 100 Ω is a current limit, not line protection).
10 k pull-ups on ~RESET (display out of reset until driven) and ~CS (no garbage clocking while the host is unconfigured — platform idle-safety convention).
Backlight select JP1 (3-pad solder jumper, default bridged 1-2):
1-2 (default): LED pin ← 100 Ω ← 3V3, always on (~20 mA).
cut 1-2, bridge 2-3: LED pin ← 100 Ω ← PMOD pin 9 for PWM dimming.
100 nF + 10 µF at the socket.

PMOD pin map (Type 2A SPI)#

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	TFT_CS	MOSI(SDA)	NC	SCK	GND	3V3	TFT_DC	TFT_RST	BL_PWM	NC	GND	3V3

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (socket orientation silkscreen with the pin-order map), DRC, fab outputs
[ ] hdl/: SPI master + ST7735 init/draw demo core
[ ] BOM export and availability check, design-review checklist