Sensor modules

AXS-024 — TFmini-S lidar carrier PMOD module

Catalog #24 in the AruviX sensor line, level L3 (UART, binary frame parsing).

Level L3 ERC clean DRC clean Fab package 6 components

3D render of the AXS-024 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	TFmini-S supply decoupling at the socket	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	10uF 10V X5R	Bulk reservoir for the lidar transmit-pulse current on the 5 V feed	`GRM21BR61A106KE19L` Murata	`C_0805_2012Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J2`	TFmini-S (JST GH 4P)	TFmini-S pigtail: 1 +5V, 2 lidar RXD (host TXD), 3 lidar TXD, 4 GND	`SM04B-GHS-TB` JST Datasheet ↗	`JST_GH_SM04B-GHS-TB_1x04-1MP_P1.25mm_Horizontal`
`J3`	EXT 5V IN	External 5 V for the TFmini-S: 1 +5V, 2 GND (common with PMOD GND)	not selected Phoenix Contact	`TerminalBlock_Phoenix_MKDS-1,5-2-5.08_1x02_P5.08mm_Horizontal`
`R1`	100R	Series protection on the lidar-driven UART TX line (3.3 V logic)	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 EXT_5V GND LIDAR_TX RXD TXD

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/sensor-modules/axs-024-lidar

Catalog #24 in the AruviX sensor line (../README.md), level L3 (UART, binary frame parsing).

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

A UART receiver in fabric on a fast (115200 baud) binary stream: sync on the 0x59 0x59 header, extract 16-bit distance and signal strength, verify the checksum — a compact frame-sync + checksum FSM lesson, plus a first honest encounter with mixed 5 V / 3.3 V system design.

The 5 V requirement (read this first)#

The TFmini-S is a 5 V-powered sensor. It draws ~140 mA average with ~200 mA peaks — far beyond what the PMOD 3V3 rail should supply, and at the wrong voltage anyway. This carrier handles it honestly:

J3 (screw terminal) takes external 5 V on the EXT_5V net; its ground terminal is common with the PMOD ground plane. Feed it from a bench supply or USB 5 V.
The TFmini-S UART logic is 3.3 V (the datasheet I/O is 3.3 V LVTTL), so its TX goes to the PMOD directly through the standard 100 Ω series resistor and the host TXD drives the lidar RX directly.
Never feed 5 V into any PMOD pin. The only 5 V on this board is between J3 and the J2 supply pin.

Design#

J2 = JST GH 4-pin horizontal (SM04B-GHS-TB), matching the TFmini-S pigtail: 1 +5V, 2 RXD (into lidar), 3 TXD (out of lidar), 4 GND. Verify the pigtail wire order against the Benewake manual before first power-up.
100 Ω series (R1) on the lidar-driven TX line.
100 nF + 10 µF decoupling on the EXT_5V feed at the connector.
PMOD Type 3 UART; TXD/RXD named from the host FPGA's viewpoint.

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	NC	TXD	RXD	NC	GND	3V3	NC	NC	NC	NC	GND	3V3

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (screw terminal + GH connector placement, 5 V keep-out from PMOD edge), DRC, fab
[ ] Pin the exact Phoenix MKDS 1,5/2-5,08 orderable part (MPN is TBD:)
[ ] Verify TFmini-S pigtail pin order against a physical unit
[ ] hdl/: UART RX core, frame parser, checksum, testbench, ECP5 demo
[ ] BOM export and availability check, design-review checklist