Lab modules

AXL-004 — Protocol breakout / exerciser PMOD module

Catalog #4 in the AruviX lab line, level L1. The sacrificial first-lab board — every signal visible, every mistake survivable. Cheapest board in the catalog; include one in every kit.

Level L1 ERC clean No layout No fab package 11 components

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J2`	PMOD SOCKET (DUT)	PMOD socket for the module under test (right-angle preferred at layout; vertical stock fp)	not selected generic	`PinSocket_2x06_P2.54mm_Vertical`
`J3`	PROBE HEADER	Labeled probe row: 1-8 = DUT1-DUT8, 9 = GND, 10 = 3V3	not selected generic	`PinHeader_1x10_P2.54mm_Vertical`
`R1`	100R	Series protection between host SIG1 and DUT1 (shorts survive)	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	100R	Series protection between host SIG2 and DUT2 (shorts survive)	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R3`	100R	Series protection between host SIG3 and DUT3 (shorts survive)	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R4`	100R	Series protection between host SIG4 and DUT4 (shorts survive)	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R5`	100R	Series protection between host SIG5 and DUT5 (shorts survive)	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R6`	100R	Series protection between host SIG6 and DUT6 (shorts survive)	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R7`	100R	Series protection between host SIG7 and DUT7 (shorts survive)	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R8`	100R	Series protection between host SIG8 and DUT8 (shorts survive)	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 DUT1 DUT2 DUT3 DUT4 DUT5 DUT6 DUT7 DUT8 GND SIG1 SIG2 SIG3 SIG4 SIG5 SIG6 SIG7 SIG8

Production status#

Schematic ERC	0 violations
PCB layout	not started
DRC	not run
Fab package	not exported
Fabricated	no — design stage only

Source: boards/lab-modules/axl-004-breakout

Catalog #4 in the AruviX lab line (../README.md), level L1. The sacrificial first-lab board — every signal visible, every mistake survivable. Cheapest board in the catalog; include one in every kit.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Nothing by itself — and that is the point. It sits between the host and any module under test so students can clip the logic-analyzer pod (AXL-001) onto J3 and watch their first I2C/SPI/UART transactions, and so the first miswired lab burns a 100 Ω resistor instead of an FPGA pin.

Design#

J1 PMOD plug → 100 Ω series on all 8 signals → J2 PMOD socket (female 2×06, Conn_02x06_Odd_Even + PinSocket_2x06_P2.54mm_Vertical, both stock-verified) where the module under test plugs in.
Plug and socket pin maps mirror per the PMOD spec (../../pmod-common/PMOD-SPEC-NOTES.md): the host receptacle numbering is the mirror image of the plug, so module pin N meets host pin N and J2 uses the identical PMOD-logical map as J1.
Every DUT-side signal also lands on J3, a labeled 1×10 probe header (8 signals + GND + 3V3). Silkscreen labels = schematic net names.
3V3/GND pass straight through (no series). No ICs → no decoupling.

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
J1 (host)	SIG1	SIG2	SIG3	SIG4	GND	3V3	SIG5	SIG6	SIG7	SIG8	GND	3V3
J2 (DUT)	DUT1	DUT2	DUT3	DUT4	GND	3V3	DUT5	DUT6	DUT7	DUT8	GND	3V3

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (plug and socket on opposite edges), DRC, fab outputs
[ ] Pin socket/header MPNs (right-angle socket for edge mount)
[ ] BOM export and availability check, design-review checklist