Sensor modules

AXS-033 — Build-your-own sigma-delta ADC lab PMOD module

Catalog #33 in the AruviX sensor line, level L4 (mixed-signal). A TLV3501 4.5 ns comparator and an RC integrator whose first-order sigma-delta modulator loop closes through the FPGA.

Level L4 ERC clean DRC clean Fab package 10 components

3D render of the AXS-033 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	10nF 50V C0G	Integrator capacitor (primary option)	`GRM1885C1H103JA01D` Murata	`C_0603_1608Metric`
`C2`	22nF DNP C0G DNP	DNP: alternative integrator capacitor for time-constant experiments	`GRM1885C1H223JA01D` Murata	`C_0603_1608Metric`
`C3`	100nF 16V X7R	Comparator supply decoupling	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`J2`	ANALOG IN	Analog input header: AIN, GND, 3V3 (input range 0..3V3)	not selected generic	`PinHeader_1x03_P2.54mm_Vertical`
`R1`	10k	Analog input series resistor into the comparator +in	`RC0603FR-0710KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	10k	Feedback resistor of the RC integrator (primary option)	`RC0603FR-0710KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R3`	4.7k DNP DNP	DNP: alternative integrator resistor for time-constant experiments	`RC0603FR-074K7L` Yageo Datasheet ↗	`R_0603_1608Metric`
`R4`	100R	Series protection on the module-driven comparator output	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`U1`	TLV3501	4.5 ns rail-to-rail comparator, push-pull output	`TLV3501AIDBVR` Texas Instruments Datasheet ↗	`SOT-23-6`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 AIN CMP_INP CMP_OUT GND SD_CMP SD_FB SD_INT

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/sensor-modules/axs-033-sigma-delta

Catalog #33 in the AruviX sensor line (../README.md), level L4 (mixed-signal). A TLV3501 4.5 ns comparator and an RC integrator whose first-order sigma-delta modulator loop closes through the FPGA.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

How an ADC actually works, by building one from three parts:

The comparator asks "is the input above the integrator average?" and its 1-bit answer (SD_CMP) is registered by a flip-flop in fabric each clock.
The registered bit drives SD_FB back into the R2/C1 integrator, so the loop forces the integrator node to track the input — the density of 1s encodes the input voltage.
A CIC (or plain averaging) decimator in fabric turns the 1-bit stream into multi-bit samples; oversampling ratio directly trades rate for ENOB.

The comparator + fabric flip-flop + RC is exactly the front end inside every commercial sigma-delta converter, just opened up for inspection.

Design#

TLV3501AIDBVR (SOT-23-6), rail-to-rail push-pull, 3V3 supply, 100 nF decoupling. SHDN is an active-high shutdown (disabled within 0.9 V of V+), so it is tied to GND for normal operation.
Analog input on J2 (AIN / GND / 3V3) through 10 kΩ into +in.
Integrator: SD_FB → R2 10 kΩ → C1 10 nF C0G to GND, node into −in. R3 (4.7 kΩ) and C2 (22 nF C0G) sit on parallel DNP pads for experimenting with the loop time constant.
Module-driven SD_CMP passes a 100 Ω series resistor.

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	SD_CMP	SD_FB	NC	NC	GND	3V3	NC	NC	NC	NC	GND	3V3

SD_CMP is module-driven; SD_FB is host-driven (the registered feedback bit). Clock the loop well above 1/(R2·C1) = 10 kHz — 1 MHz+ works nicely.

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (keep the R2/C1 node tight against U1), DRC, fab outputs
[ ] hdl/: loop register + CIC decimator, ENOB-vs-OSR measurement demo
[ ] BOM export and availability check, design-review checklist