Comms modules

AXC-006 — ATECC608B crypto element PMOD module

Catalog #6 in the AruviX comms line, level L3 (I2C). Microchip ATECC608B secure element: hardware ECC P-256 keys that never leave the die. Anchors the security mini-curriculum with AXC-001..004 (and the deferred fingerprint carrier in the sensor-line backlog).

Level L3 ERC clean DRC clean Fab package 7 components

3D render of the AXC-006 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`C1`	100nF 16V X7R	U1 decoupling	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`JP1`	SDA PULL-UP	Cut to remove the SDA pull-up when chaining modules	—	`SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`
`JP2`	SCL PULL-UP	Cut to remove the SCL pull-up when chaining modules	—	`SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`
`R1`	4.7k	I2C SDA pull-up	`RC0603FR-074K7L` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	4.7k	I2C SCL pull-up	`RC0603FR-074K7L` Yageo Datasheet ↗	`R_0603_1608Metric`
`U1`	ATECC608B-SSHDA-T	CryptoAuthentication secure element, ECC P-256, I2C, SOIC-8	`ATECC608B-SSHDA-T` Microchip Datasheet ↗	`SOIC-8_3.9x4.9mm_P1.27mm`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 GND SCL SCL_PU SDA SDA_PU

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/comms-modules/axc-006-crypto

Catalog #6 in the AruviX comms line (../README.md), level L3 (I2C). Microchip ATECC608B secure element: hardware ECC P-256 keys that never leave the die. Anchors the security mini-curriculum with AXC-001..004 (and the deferred fingerprint carrier in the sensor-line backlog).

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Secure boot (verify AruviOS images), signing (sign telemetry before AXC-003 publishes it over MQTT), peer authentication for the radio modules, and a non-trivial I2C driver: the wake-pulse protocol quirk — the part sleeps hard, and a plain START does not wake it. The driver must hold SDA low for

60 µs (tWLO), release, wait 1.5 ms (tWHI), then poll for the 0x11 wake

response. The atecc_i2c HDL core owns this sequence.

Design#

Standard AXS I2C pattern: 4.7 k pull-ups behind JP1 (SDA) / JP2 (SCL) solder jumpers, bridged by default — cut when another chained module provides the pull-ups. Bus repeated on PMOD pins 9/10 for daisy-chaining.
Address convention, stated clearly: the datasheet's 0xC0 is the 8-bit write address; in 7-bit terms (what AruviOS drivers use) the device is at 0x60. Fixed — no address jumper exists for this part.
SOIC-8 (ATECC608B-SSHDA-T); pins 1–3 and 7 are true no-connects.
100 nF decoupling; 3.3 V only.

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	NC	NC	SCL	SDA	GND	3V3	NC	NC	SCL	SDA	GND	3V3

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (20 × 25 mm outline), DRC, fab outputs
[ ] hdl/: atecc_i2c core with wake-pulse handling, testbench
[ ] Provisioning lesson: slot configuration is one-time-lockable — write the config walkthrough before anyone locks a dev board by accident
[ ] BOM export and availability check, design-review checklist