I/O modules

AXO-018 — DS3231 RTC + coin cell PMOD module

Catalog #18 in the AruviX output line, level L3 (I2C). Battery-backed timekeeping: BCD registers, alarms, and state that survives power-off — plus the data-logger timestamp source for the sensor line.

Level L3 ERC clean DRC clean Fab package 13 components

3D render of the AXO-018 PCB — Rendered from the PCB layout. No physical board has been manufactured.

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Ref	Value	What it does on this board	Part number	Footprint
`BT1`	CR2032	CR2032 backup cell in Keystone 3034 SMD 20 mm coin-cell holder	`3034` Keystone Datasheet ↗	`BatteryHolder_Keystone_3034_1x20mm`
`C1`	100nF 16V X7R	VCC decoupling at U1	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`C2`	100nF 16V X7R	VBAT decoupling per DS3231 datasheet (0.1 uF close to pin 6)	`GRM188R71C104KA01D` Murata	`C_0603_1608Metric`
`J1`	PMOD PLUG 2x6	PMOD peripheral plug (Digilent spec 1.2)	not selected generic	`PinHeader_2x06_P2.54mm_Horizontal`
`JP1`	SDA PULL-UP	Cut to remove the SDA pull-up when chaining modules	—	`SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`
`JP2`	SCL PULL-UP	Cut to remove the SCL pull-up when chaining modules	—	`SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`
`R1`	4.7k	I2C SDA pull-up	`RC0603FR-074K7L` Yageo Datasheet ↗	`R_0603_1608Metric`
`R2`	4.7k	I2C SCL pull-up	`RC0603FR-074K7L` Yageo Datasheet ↗	`R_0603_1608Metric`
`R3`	10k	Pull-up for the open-drain ~INT/SQW output	`RC0603FR-0710KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R4`	100R	Series protection on the module-driven ~INT line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R5`	10k	Pull-up for the open-drain 32 kHz output (verified open collector in the symbol/datasheet)	`RC0603FR-0710KL` Yageo Datasheet ↗	`R_0603_1608Metric`
`R6`	100R	Series protection on the module-driven 32 kHz line	`RC0603FR-07100RL` Yageo Datasheet ↗	`R_0603_1608Metric`
`U1`	DS3231MZ	I2C RTC, MEMS resonator +/-5 ppm, battery backup, 2 alarms, addr 0x68	`DS3231MZ+TRL` Analog Devices Datasheet ↗	`SOIC-8_3.9x4.9mm_P1.27mm`

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 CLK32K CLK32K_OC GND RTC_INT_N RTC_INT_OC SCL SCL_PU SDA SDA_PU VBAT

Production status#

Schematic ERC	0 violations
PCB layout	complete
DRC	0 violations
Fab package	exported (24 gerbers + drill + CPL + BOM)
Fabricated	no — design stage only

Source: boards/io-modules/axo-018-rtc

Catalog #18 in the AruviX output line (../README.md), level L3 (I2C). Battery-backed timekeeping: BCD registers, alarms, and state that survives power-off — plus the data-logger timestamp source for the sensor line.

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

BCD date/time arithmetic, alarm interrupts on ~INT, the battery-handover story (the chip swaps to VBAT automatically and keeps counting), aging-offset trims, and a 32.768 kHz reference for frequency-measurement exercises.

Part substitution (documented)#

The catalog said "DS3231 (TCXO)". The TCXO part is the SO-16W DS3231SN, which has no stock KiCad symbol; the stock Timer_RTC:DS3231MZ is the SOIC-8 MEMS-resonator variant (±5 ppm vs the TCXO's ±2 ppm) — same register map, same fixed I2C address 0x68, same VBAT behaviour. Fitted part: DS3231MZ+TRL (Analog Devices). ±5 ppm is ≈ ±2.6 min/year — fine for the curriculum; a rev could move to the SN with a contributed symbol.

Design#

Standard line I2C pattern: 4.7 k pull-ups through JP1 (SDA) / JP2 (SCL) solder jumpers (cut when another module on the chain provides pull-ups); bus repeated on PMOD 9/10. Address is fixed 0x68 — no address jumper exists on this chip.
~INT/SQW (open-drain, verified from the symbol/datasheet): 10 k pull-up (R3) + 100 R series (R4) → PMOD pin 1, net RTC_INT_N.
32KHZ output (open-drain, verified): 10 k pull-up (R5) + 100 R (R6) → PMOD pin 2, net CLK32K. Runs from VBAT too (EN32kHz bit), so a scope shows it ticking with the module unplugged.
~RST (pin 4): pushbutton-reset input/output with an internal 50 k pull-up; unused here and left open per the datasheet (marked no-connect).
Battery: CR2032 in a Keystone 3034 SMD 20 mm holder (stock footprint Battery:BatteryHolder_Keystone_3034_1x20mm, symbol Device:Battery_Cell). The cell itself ships separately (kit note).
100 nF on VCC (C1) and 100 nF on VBAT (C2) per the DS3231 datasheet; VBAT carries its own PWR_FLAG since the battery is a source net.

PMOD pin	1	2	3	4	5	6	7	8	9	10	11	12
Net	RTC_INT_N	CLK32K	SCL	SDA	GND	3V3	NC	NC	SCL	SDA	GND	3V3

Type 6 extended I2C; both module-driven lines are open-drain with on-module 10 k pull-ups per the line rule.

Regenerate#

python3 generate_design.py

Remaining for release#

[ ] PCB layout (coin-cell holder clear of the PMOD plug, battery polarity silk), DRC, fab outputs
[ ] hdl/: I2C master reuse, BCD clock demo on the 7-seg module, alarm-interrupt demo
[ ] BOM export and availability check, design-review checklist
[ ] Decide kit policy for shipping CR2032 cells (transport regulations)