Circuit review & bench-test guide

AXO-018 — DS3231 RTC + coin cell PMOD module

Design-stage — board not yet fabricated

Document purpose#

Component-level explanation and bench-test plan for axo-018-rtc, from generate_design.py, the module README.md, and the Analog Devices DS3231MZ datasheet. Never fabricated; values are verification targets.

1. What the board does#

A battery-backed real-time clock on I2C, with a coin cell for timekeeping through host power loss. It teaches BCD time registers, alarms, and battery-backed state. The MZ variant is the MEMS-resonator part (±5 ppm), a documented substitution for the catalog's TCXO SN (±2 ppm).

PMOD J1  SCL/SDA (3/4, JP1/JP2 pull-ups) ─> U1 DS3231MZ (addr 0x68)
         INT/SQW (1, 10k PU + 100R) ; 32kHz (2, 10k PU + 100R)
         CR2032 coin cell ─> U1 VBAT

2. Safety and scope boundaries#

3.3 V logic. PMOD host or 3.3 V bench supply (~1 mA active, µA on battery).
Coin cell: observe polarity; never reverse-charge a primary CR2032. The DS3231 does not charge the cell (correct — it's a primary cell).
Unreleased prototype.

4. Interfaces#

J1 PMOD Type 6 extended: 1 INT/SQW, 2 32kHz, 3 SCL, 4 SDA, 9/10 bus repeat, 5/11 GND, 6/12 3V3.
JP1/JP2 4.7 k I2C pull-ups. Coin-cell holder for VBAT.

5. Component-by-component review#

U1 DS3231MZ (SOIC-8): I2C RTC/TCXO. Fixed address 0x68. Integrated MEMS resonator + temperature compensation; on-chip 32 kHz output and a programmable INT/SQW. If absent/dead: no ACK. If VBAT is reversed/absent: time is lost on host power-down (the whole point of the cell).
INT/SQW network: 10 kΩ pull-up + 100 Ω series: the alarm/square-wave output is open-drain; pull-up sets its high, 100 Ω protects the chip-driven line. If pull-up absent: line floats. If series R absent: host miswire shorts it.
32kHz network: 10 kΩ pull-up + 100 Ω series: the 32.768 kHz output is also open-drain; same rationale. If pull-up absent: no clock edge seen.
CR2032 holder + cell: backup power. If the cell is dead/absent: the oscillator-stop flag (OSF) sets on the next power-up, signalling time was lost.
C1 100 nF: VCC decoupling. If absent: I2C glitches.

6. Datasheet summary (DS3231MZ)#

VCC 2.3–5.5 V; VBAT 2.3–5.5 V (primary cell, not charged). I2C 400 kHz, address 0x68.
Registers: seconds/min/hours/day/date/month/year in BCD (0x00–0x06), Alarm1 (0x07–0x0A), Alarm2 (0x0B–0x0D), Control 0x0E, Status 0x0F (bit7 = OSF oscillator-stop flag, bit3 EN32kHz), Aging 0x10, Temp 0x11–0x12 (0.25 °C).
INT/SQW: alarm interrupt or 1 Hz/1.024/4.096/8.192 kHz square wave (Control register). Separate 32kHz pin.
Accuracy: MZ variant ±5 ppm 0–40 °C (≈ ±2.5 min/yr) — worse than the ±2 ppm SN; adequate for a clock lesson.

7. Expected values before bench testing#

Idle SDA/SCL: 3.3 V. ACK at 0x68.
First power-up with a fresh cell never set: OSF = 1 (status 0x0F bit7) — expected, clear it after setting time.
32kHz pin toggles at 32.768 kHz when enabled.

8. Manual review checklist#

[ ] JP1/JP2 bridged; INT/SQW and 32kHz each have 10 k pull-up + 100 Ω.
[ ] Coin-cell holder polarity correct.
[ ] C1 present.

9. Ordered bench-test procedure#

A. Unpowered: verify pull-ups, INT/32kHz networks, cell-holder polarity; no rail short. Insert a fresh CR2032, confirm ~3 V at VBAT.

B. Power, idle: 3.3 V. Bus idle-high; ACK at 0x68.

C. Status/OSF: read 0x0F; expect OSF=1 on a never-set part. Set the time (write 0x00–0x06 in BCD), then clear OSF.

D. Timekeeping: read time twice a minute apart; confirm it advances correctly in BCD.

E. 32kHz + SQW: enable the 32kHz output (status bit3); scope pin 2 → 32.768 kHz. Set Control for 1 Hz SQW; scope INT/SQW → 1 Hz.

F. Battery switchover: with time set, remove 3.3 V for ~30 s, restore; read time — it should have advanced (ran on the cell) and OSF stays 0. If OSF sets, the cell/holder is bad.

10. Troubleshooting map#

No ACK: pull-ups cut, or wrong rail.
Time resets on power cycle: dead cell, reversed holder, or VBAT open (OSF will be 1).
No 32kHz/SQW edge: output not enabled, or pull-up missing (open-drain).
BCD confusion: reading hex where BCD is expected — firmware, not a fault.

11. Bench record template#

Board: axo-018  ACK 0x68: [ ]  VBAT: __ V
OSF initial: __  time set + OSF cleared: [ ]
32kHz on pin 2: [ ]  1Hz SQW on INT: [ ]
Battery-hold survives power cycle (OSF stays 0): [ ]
Notes:

12. Review conclusion#

The distinctive test is the battery-switchover: pull host power, restore, and confirm time advanced with OSF still 0 — that proves the cell path. The MZ ±5 ppm accuracy is a documented substitution from the ±2 ppm SN; both are BCD DS3231s to the driver. INT/SQW and 32kHz are open-drain, so their pull-ups are load-bearing.