← AXL-002

Circuit review & bench-test guide

AXL-002 — Oscilloscope front end dual-PMOD module (AD9280)

Document purpose#

This document explains the axl-002-scope prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic, 2026-07-12), the README, the TI OPA356 datasheet, and the reviewer's knowledge of the ADI AD9280 datasheet (which could not be fetched during this review — see Section 6).

The board is a design-stage prototype. The schematic is generated and ERC clean (reports/erc.rpt, 2026-07-12: 0 errors / 0 warnings, with KiCad's single-global-label, four-way-junction, SPICE, and footprint-filter checks ignored) and the netlist has been reviewed, but PCB layout has not started and no board has been fabricated or assembled. There is no first-article bench result of any kind. Every expected value below is a design target to verify, not proof that an assembled board works.

1. What the board does#

The board is a dual-PMOD (two adjacent 12-pin sockets on 0.9" centers) oscilloscope front end around an ADI AD9280ARSZ 8-bit 32 MSPS parallel pipeline ADC, sampled at 25 MHz by a host-driven clock. The analog path is rev-1 DC-coupled, low-voltage only: a signal arrives on a 1x2 header (J2) or the parallel BNC (J4), passes an optional 910k/100k = 10.1:1 divider (solder jumper JP3, bridged = 1:1), is clamped to the rails by a BAT54S Schottky pair, and is buffered by an OPA356 unity follower into AIN. The ADC runs in top/bottom reference mode (MODE = AVDD) with its internal 1.25 V bandgap scaled by R3/R4 to VREF ≈ 2.02 V (JP4 selectable to 1.25 V), so the native input span is 0–2.02 V (≈0–20.4 V with the divider). Eight data bits and OTR leave through 100 Ω series resistors to PMOD A; PMOD B carries CLK in, OTR, and STBY.

There is no AC coupling, no offset generator, no negative range, and no isolation — a silkscreen warning is a release requirement. It teaches triggering, decimation, and pre-trigger ring buffers (scope_capture core), pairing with AXL-003 (wavegen) as its own test source and AXO-007 (VGA) as its display.

Functional block diagram#

J2 header ──┬── SIG_IN ──┬── R1 910k ──┬── VIN ── U2 OPA356 ── AIN ── U1 AD9280
J4 BNC   ───┘            └── JP3 ──────┤          (unity)              (8b, 25 MHz)
                          (bridged=1:1)├── R2 100k ── GND
                                       └── D1 BAT54S (GND-0.3 .. 3V3+0.3 clamp)

 VREF ── R3 6.2k ── REF_DIV ── R4 10k ── GND     U1 straps: MODE = AVDD_F,
 JP4: REFSENSE ── 1-2 REF_DIV (VREF≈2.02V,      REFTS = VREF, REFBS = GND,
      default) / 2-3 VREF (VREF=1.25V)          CLAMP/CLAMPIN/THREE-STATE = GND
 3V3 ── R5 10R ── AVDD_F (+C7/C8)               STBY_S: R6 10k to GND, R16 100R to J3-3

 U1 D0-D7/OTR ── R7-R15 100R ── J1 (PMOD A: D0-D7)
 J3 (PMOD B): 1 CLK (host 25 MHz out), 2 OTR, 3 STBY

2. Safety and scope boundaries#

• The analog input is DC-coupled and unipolar. Native (JP3 bridged) safe and useful range is 0–2 V; the BAT54S clamp and the OPA356's internal diodes protect against modest overdrive only. Never connect mains-derived, floating-at-line, or high-energy sources; this is not a general scope probe input.
• In 1:1 mode the clamp is directly on the input node — an external source above ~3.6 V or below ~−0.3 V drives current into the clamp with only the source's own impedance limiting it. Keep any deliberate overdrive behind an external series resistor (Section 9.E).
• In 10:1 mode (JP3 cut) the working range is ≈0–20 V and R1 (910k) limits clamp current, but R1 is a 0603 part: keep inputs below ±30 V for bench work regardless of the clamp math.
• Never plug the module into 5 V PMOD ports; every rail and strap assumes 3.3 V.
• Standalone bench work uses a current-limited 3.3 V supply (limit ~100 mA; expected module draw is ~40 mA, Section 7).
• Earth-referenced oscilloscope grounds clip only to board GND — and the BNC shell IS board GND, so a grounded source ties the module to earth.
• A clean code readout is not a calibration: the reference chain, divider, and buffer are unverified and every accuracy number here is a design target.

3. Power and control sequence#

1. 3V3 and GND arrive on both PMOD plugs (pins 5/11 and 6/12 of J1 and J3); C11 (10 µF) is the module bulk, C9 decouples DRVDD, C10 decouples U2.
2. AVDD is filtered from 3V3 through R5 (10 Ω) + C7 (10 µF) + C8 (100 nF) — a documented substitution for a ferrite bead (none stock-verified in the platform BOM). Note the ~0.2–0.3 V IR drop this implies at the ADC's analog supply current (Section 7).
3. The AD9280's internal 1.25 V bandgap starts; with JP4 bridged 1-2, REFSENSE sits on the R3/R4 tap and the reference amplifier servos VREF to 1.25 V × (1 + 6.2k/10k) ≈ 2.02 V. MODE = AVDD selects top/bottom reference mode; REFTS = VREF and REFBS = GND set the input span to 0 V..VREF. C3/C4 (100 nF each) and C5 (10 µF across) settle the REFTF/REFBF force nodes per the datasheet decoupling.
4. R6 (10 kΩ) holds STBY_S low: the ADC runs by default. The host may drive STBY high through J3 pin 3 and R16 (100 Ω) to power down the core. THREE-STATE, CLAMP, and CLAMPIN are tied low (outputs always driven, video clamp disabled).
5. U2 (OPA356) buffers VIN to AIN with unity gain; the ADC samples AIN on the host-supplied CLK (25 MHz from the ECP5 fabric; the part is rated 32 MSPS). Data appears on D0–D7 after the pipeline latency (three clock cycles per the datasheet — re-verify, Section 6) and OTR flags out-of-range samples.
6. Nothing converts without a host clock: with CLK static the pipeline holds stale/undefined data. All bring-up code reads assume a running clock.

4. Interfaces and pin maps#

This is a dual-PMOD module: both connectors must plug into adjacent host sockets on 0.9" centers, and CLK must come from the clock-capable host pin tracked in boards/BACKLOG.md.

Jumper configuration review:

Never leave JP4 fully open (REFSENSE floating selects an undefined reference configuration) and never bridge all three pads (shorts REF_DIV to VREF, collapsing the divider to VREF ≈ 1.25 V through a loaded tap).

5. Component-by-component review#

Every reference designator in generate_design.py appears below. Capacitor numbering starts at C3 (there is no C1/C2 — a cosmetic refdes gap, not a missing part). #FLG01–#FLG03 are ERC power-flag pseudo-components on 3V3, GND, and AVDD_F; they have no physical footprint and are listed only for completeness.

6. Datasheet summary and design interpretation#

Consulted directly: TI OPA356/OPA2356 datasheet SBOS212A (November 2001), <https://www.ti.com/lit/ds/symlink/opa356.pdf>.

The AD9280 datasheet could not be fetched during this review (both <https://www.analog.com/media/en/technical-documentation/data-sheets/AD9280.pdf> and <https://www.analog.com/en/products/ad9280.html> timed out). The AD9280 rows below are written from the reviewer's knowledge of that datasheet (Rev. B era) and the design script's own annotations; every AD9280 fact must be re-verified against the actual datasheet before layout release and before trusting any bench limit derived from it. The BAT54S facts trace to the Nexperia datasheet URL recorded in the design script (<https://assets.nexperia.com/documents/data-sheet/BAT54_SER.pdf>), not to a fresh fetch.

Check the latest datasheet revisions before procurement; the AD9280 rows in particular are unverified in this document.

7. Expected values before bench testing#

Targets assume 3V3 = 3.300 V, JP3 bridged (1:1), JP4 1-2 (VREF ≈ 2.025 V), 1% resistors, and a running 25 MHz clock unless stated. All are design targets, not measured results; the ones marked (re-verify) depend on AD9280 datasheet numbers that could not be confirmed.

Known-DC-level code math#

General formula (top/bottom mode, V_bottom = REFBS = 0 V, V_top = VREF):

code = (Vin − V_bottom) / (V_top − V_bottom) × 255
     = Vin / 2.025 × 255            (JP3 bridged, JP4 1-2)
     = Vin / (10.10 × 2.025) × 255  (JP3 cut, 10:1)

Worked example: with the nominal 0–2 V span, 1.0 V in reads code ~128 of 255 on an ideal 2.000 V span; with this board's exact 2.025 V VREF the nominal expectation is code 126. Tolerance bounds below use ±4% of reading ± 3 LSB — the Section 9.F budget with placeholder AD9280 terms, to be tightened once the datasheet numbers are confirmed.

10:1-mode bands add the ±1.8% divider-ratio tolerance to the 1:1 budget.

8. Manual schematic and assembly review checklist#

• Confirm U1 orientation and the ARSZ suffix; the SSOP-28 footprint was assigned manually (the stock symbol has none) — verify pad 1 and pitch against the physical part before ordering stencils.
• Confirm U2 orientation (SOIC-8; pins 1/5/8 are NC on the OPA356AID).
• Confirm D1 (BAT54S, SOT-23) orientation: series pair with COM on VIN, anode end to GND, cathode end to 3V3.
• Verify JP3 bridged and JP4 bridged 1-2 (pads 2-3 open, no three-pad bridge).
• Measure R3 = 6.2 k (VREF–REF_DIV), R4 = 10 k (REF_DIV–GND), R5 = 10 Ω (3V3–AVDD_F), R6 = 10 k (STBY_S–GND), R16 = 100 Ω (STBY_S–J3-3).
• Measure R1 = 910 k (SIG_IN–VIN, JP3 cut to read it), R2 = 100 k (VIN–GND).
• Buzz all nine 100 Ω series paths: U1 data pins through R7–R14 to J1 pins 1–4/7–10 in order D0–D7, and OTR through R15 to J3-2.
• Buzz J2 pin 1 to the J4 center pin (parallel inputs) and J2 pin 2 to the BNC shell (GND).
• Check C3/C4/C5 land directly at REFTF/REFBF and C8 at the AVDD pin during layout review (layout not yet started — carry forward).
• Carry forward the silkscreen warning requirement: DC-coupled, 0–2 V (0–20 V at 10:1), no isolation.
• Confirm no solder bridges on the 0.65 mm-pitch SSOP-28, especially the reference cluster (REFSENSE/VREF/REFTS/REFBS/REFTF/REFBF are adjacent).

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host identity, jumper states, measured 3V3, and the DMM used for reference checks.

Two bench contexts are used throughout: (a) PMOD host — both plugs seated in two adjacent 3.3 V PMOD ports on the ECP5 host (ULX3S-class), CLK from a clock-capable fabric pin, codes captured by a small HDL harness; (b) standalone — 3V3/GND from a current-limited bench supply (100 mA limit), CLK from a 3.3 V function/pulse generator, D0–D7/OTR captured on a logic analyzer.

A. Unpowered inspection and resistance tests#

1. Complete the Section 8 checklist under magnification.
2. Measure 3V3-to-GND resistance in both polarities; investigate < 1 kΩ.
3. Measure AVDD_F-to-GND (through R5 it should track the 3V3 reading plus 10 Ω) and VREF-to-GND (≈16.2 kΩ, the R3+R4 string, once the internal circuits are out of the picture — record the actual value as a fingerprint).
4. Jumper-position resistance checks at J2 (probe pin 1 to pin 2):

• JP3 bridged: ≈ 100 kΩ (R2), and SIG_IN-to-VIN ≈ 0 Ω.
• JP3 cut: ≈ 1.01 MΩ (R1 + R2), and SIG_IN-to-VIN ≈ 910 kΩ.

1. Diode-check D1 from the VIN node: ~0.3 V drop to 3V3 (positive lead on VIN) and ~0.3 V drop from GND (positive lead on GND side); open in reverse.

B. First power, no clock#

1. Power in context (b) first. Supply current ≈ 40 mA (Section 7); anything over ~60 mA or under ~10 mA is abnormal — stop.
2. Measure the reference ladder: VREF ≈ 2.025 V, REF_DIV ≈ 1.25 V, REFTS ≈ 2.025 V, REFBS = 0 V, REFTF/REFBF ≈ their sense counterparts. A REF_DIV reading of 1.25 V is the single best evidence the internal reference and REFSENSE strapping work as designed. If VREF reads ≈1.25 V instead, suspect JP4 bridged 2-3 or a three-pad bridge.
3. Measure AVDD_F ≈ 3.0 V (> 2.7 V required). Record the R5 drop as the measured I_AVDD.
4. Ground the input (JP3 bridged, J2 shorted): VIN and AIN both 0 V ± 10 mV. Apply 1.000 V from a bench source: VIN = AIN = 1.000 V ± Vos (buffer follows).
5. Drive STBY (J3-3) high: supply current drops to the standby target; release: current returns.
6. Repeat step 1–3 in context (a) with the FPGA unconfigured.

C. Static DC code readout (known-DC-level test)#

Context (a) with a minimal capture harness (25 MHz clock, register D0–D7 and OTR every cycle), or context (b) with a 1–25 MHz generator clock and logic analyzer. Remember the 3-cycle pipeline latency (re-verify) when aligning.

1. Input grounded: code 0–3 expected (offset + Vos), OTR may assert at code 0.
2. Apply DMM-verified DC levels per the Section 7 table (0.1, 0.5, 1.0, 1.5, 1.8, 2.0 V). Compare each captured code (average ≥ 1000 samples) against the acceptance band. 1.000 V must read ~126 (128 on an ideal 2.000 V span).
3. Record the 1.8–2.0 V behavior separately: deviation growing above 1.8 V is the OPA356 CM-range limitation showing (Section 6), not necessarily an ADC fault.
4. Confirm OTR = 1 exactly when the code rails at 0 or 255.

D. 10:1 divider position checks#

1. Power off. Cut JP3. Repeat the Section 9.A.4 resistance checks for the cut position (1.01 MΩ input, 910 kΩ across the jumper).
2. Power on, apply 10.00 V (DMM-verified): VIN ≈ 0.990 V, code ≈ 125.
3. Walk 5/10/15/20 V per the Section 7 10:1 table.
4. Compute the measured scale factor (Vin/VIN) and record it against the 10.10 nominal ± 1.8% band.
5. Re-bridge JP3 and re-verify one 1:1 point (1.000 V → ~126) to prove the rework.

E. Clamp/protection diode test (controlled overdrive)#

The clamp must conduct where expected and nowhere else. All overdrive goes through an external 10 kΩ series resistor in 1:1 mode; the module's own ~40 mA draw absorbs the injected current without pumping the rail, but monitor 3V3 anyway.

1. 1:1 mode, +5.0 V source through 10 kΩ into J2-1: VIN clamps at ≈ 3.6–3.7 V (3V3 + one VF). Clamp current = (5.0 − 3.65)/10 kΩ ≈ 135 µA — measure it as the drop across the external resistor. Code reads 255, OTR = 1, 3V3 unchanged.
2. −5.0 V through 10 kΩ: VIN clamps at ≈ −0.3 to −0.4 V; current ≈ (5.0 − 0.35)/10 kΩ ≈ 465 µA. Code 0, OTR = 1.
3. 10:1 mode (JP3 cut), +30 V applied directly: VIN ≈ 2.97 V unclamped — below the clamp threshold, so no clamp current flows; code 255, OTR = 1. This proves R1 alone keeps 30 V safe. (The clamp would begin conducting only above ≈ 3.65 × 10.1 ≈ 37 V at the input; at 50 V the current would be (50 − 3.65)/910 kΩ ≈ 51 µA — do not test above 30 V on the bench; 0603 voltage ratings and creepage are unreviewed.)
4. After each overdrive, re-run one Section 9.C point to confirm no degradation.

F. Instrument validation against a known source#

This is an instrument board: before any measurement made with it is quoted, validate it against a calibrated reference.

1. Source: a calibrated voltage reference or a bench supply verified at the test point by a DMM with current calibration (record DMM ID and cal date).
2. Tolerance budget for the acceptance band (all worst-case terms added):

• divider ratio (10:1 mode only): ±1.8% (two 1% resistors)
• VREF: bandgap tolerance (re-verify from datasheet) + ±0.8% (R3/R4 ratio, 1% parts)
• ADC gain + offset error: placeholder ±2% ± 2 LSB (re-verify)
• buffer Vos: ±9 mV max = ±1.1 LSB Combined placeholder budget: ±4% of reading ± 3 LSB (1:1), ±6% ± 3 LSB (10:1). Recompute both once the AD9280 datasheet numbers are confirmed, and tighten to the real budget.

1. Apply 5 DMM-verified levels spanning 10–90% of each range (both JP3 positions); every averaged code must fall inside the computed band. Record the worst deviation as the module's provisional accuracy figure.
2. Restrict the quoted validated range to ≤1.8 V at the buffer until the CM-limit behavior (9.C.3) is characterized.

G. Staircase/ramp linearity with AXL-003 (wavegen)#

Uses the companion AXL-003 wavegen module as the source and the FPGA host as the capture engine — the intended self-test pairing.

1. Drive a slow full-scale ramp (or the R-2R staircase) from AXL-003 into J2, 1:1 mode: period ≥ 10 ms so every output code is visited many times at 25 MSPS (decimate in the capture core).
2. Capture ≥ 10 full periods of codes on the host.
3. Monotonicity: on the rising ramp, codes must never decrease (beyond 1-code noise). Every code 1–250 must appear (no missing codes — a DNL proxy).
4. INL-style check: fit a straight line to code-vs-time over the linear ramp segment; deviation of the code-transition points from the fit should stay within ±2 LSB below code ~227, and the region above (U2 CM limit) is recorded separately.
5. Cross-check the ramp endpoints against a scope on VIN so wavegen nonlinearity is not misattributed to this board.

H. Dynamic and host-integration tests#

1. Scope CLK at J3-1 at the ADC pin side of the connector: clean 25 MHz, 3.3 V CMOS, no double-clocking (ringing through the un-terminated PMOD interconnect is a known risk — record the waveform).
2. Scope one data line (e.g. D7 after R14) while converting a mid-scale DC level: stable levels, transitions only at clock edges.
3. Slow-clock regression: repeat 9.C at 1 MHz CLK; codes must match the 25 MHz results within noise (pipeline parts have minimum clock specs — re-verify the AD9280 floor before going far below 1 MHz).
4. STBY functional test under clock: assert J3-3 high mid-capture; data collapses; release; data returns after the pipeline refills.
5. Sine capture from AXL-003 for the full scope demo (trigger, decimation, pre-trigger ring) — beyond bring-up scope; record results with the HDL revision.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design is a faithful implementation of the AD9280 single-supply 0–2 V application: correct top/bottom reference strapping (MODE = AVDD, REFTS = VREF, REFBS = GND) with the REFSENSE divider giving a selectable 2.02 V/1.25 V span, the full datasheet reference decoupling, a documented RC substitution for the missing ferrite bead, series protection on all nine ADC-driven lines, and a sensible default-run STBY strap. The front end is honest about being rev-1: DC-coupled, unipolar, and jumper-scaled, with the BAT54S clamp placed where it protects the buffer.

The principal open risks: (1) the OPA356 input common-mode ceiling (~1.8 V at 3.3 V) sits below the 2.02 V span top — the top ~11% of the range is outside the buffer's specified input range and must be characterized or the span dropped to 1.25 V; the README's "rail-to-rail" description holds only for the output. (2) The AD9280 datasheet could not be fetched for this review — every reference-mode, latency, power, and accuracy figure above is from memory and must be re-verified. (3) No PCB exists: reference-cluster and AVDD decoupling placement, the dual-plug 0.9" mechanical alignment, and 25 MHz clock/data integrity over un-terminated PMOD interconnect are all unverified. (4) The clamp returns overdrive current into the 3V3 rail, which is only safe while the module's own draw exceeds the injected current. (5) The ~0.3 V drop across R5 leaves AVDD ≈ 3.0 V — legal but worth a measured confirmation. (6) Every expected code and voltage in this guide is calculated, not measured on hardware.