← AXL-001

Circuit review & bench-test guide

AXL-001 — 8-channel logic analyzer pod PMOD module

Document purpose#

This document explains the axl-001-la-pod prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic, 2026-07-12), the README, the TI SN74LVC245A datasheet, and the Digilent Pmod Interface Specification.

The board is a design-stage prototype. The schematic is generated and ERC clean (reports/erc.rpt, 2026-07-12: 0 errors / 0 warnings, with KiCad's single-global-label, four-way-junction, SPICE, and footprint-filter checks excluded) and the netlist has been reviewed, but PCB layout has not started and no board has been fabricated or assembled. There is no first-article bench result of any kind, no BOM export, and the companion HDL (la_capture, sump_uart) does not exist yet. Every expected value below is a design target to verify, not proof that an assembled board works.

1. What the board does#

The board is a 12-pin PMOD module carrying a TI SN74LVC245A octal bus transceiver used as a one-way probe buffer: eight logic-analyzer probe tips enter header J2, pass a 100 kΩ idle pull-down and a 1 kΩ series fault-current-limit resistor per channel into the transceiver's B port (VCC = 3.3 V), and leave the A port through 100 Ω series resistors onto PMOD pins 1–4 and 7–10. DIR is hardwired low (B-to-A only) and ~OE is hardwired low (always enabled), so the pod is a fixed unidirectional buffer.

The deciding part-selection fact (per the lab-line README review) is that LVC inputs accept up to 5.5 V regardless of VCC, so the pod can probe 5 V DUTs while presenting clean 3.3 V CMOS levels to the FPGA host. The pod itself contains no sampling, triggering, or memory: it is a buffer, not a sampler. Capture is done by the FPGA host running the (not yet written) la_capture core, dumped over UART in SUMP protocol so PulseView connects directly — that entire instrument claim currently rests on unwritten HDL.

Functional block diagram#

J2 PROBE POD (2x05)                U1 SN74LVC245A (TSSOP-20, VCC = 3V3)
 1-8  PROBE0..7 ──┬── R1-R8 100k ── GND      (idle pull-down at the tip)
                  └── R9-R16 1k ──> CHx_IN ──> B port  (5 V-tolerant inputs)
 9/10 GND (probe grounds)                       │ DIR = GND (B->A)
                                                │ ~OE = GND (always on)
J1 PMOD (Type 1A GPIO)                          v
 1-4  CH0-CH3 <── R17-R20 100R <── CHx_BUF <── A port  (3.3 V CMOS out)
 7-10 CH4-CH7 <── R21-R24 100R <──┘
 5/11 GND, 6/12 3V3 ── C1 100n + C2 1u ── decoupling

2. Safety and scope boundaries#

• Probe inputs are safe to 5.5 V, hard-limited at 6.5 V absolute maximum (datasheet Section 7.1: V_I range −0.5 to 6.5 V; recommended V_I 0 to 5.5 V regardless of VCC). 3.3 V and 5 V logic DUTs are in scope. 12 V, 24 V, automotive, or mains-adjacent nodes are out of scope: LVC 5 V tolerance works by omitting the positive input clamp diode, so the 1 kΩ series resistor does not save the input above 6.5 V — there is nothing to clamp into.
• Negative excursions are clamped by the input diode to GND; abs max input clamp current I_IK is −50 mA at V_I < 0. The 1 kΩ series resistor keeps a −5 V miswire to roughly (5 − 0.5)/1 k ≈ 4.5 mA — safe, but not a license to probe negative rails deliberately.
• 1.8 V and 2.5 V DUT logic is not reliably captured: V_IH min is 2.0 V at VCC 2.7–3.6 V, so a 1.8 V high never registers and a worst-case 2.5 V CMOS high (V_OH min ≈ 2.0 V) sits exactly on the threshold.
• The FPGA host must never drive the CH0–CH7 PMOD pins. ~OE is tied low, so the A port is always driven; abs max on a driven output is VCC + 0.5 V and contention through the 100 Ω resistors (~33 mA at 3.3 V) approaches the ±50 mA continuous-output abs max. The capture HDL must configure all eight pins as inputs before the pod is attached.
• Probe grounds (J2 pins 9/10) connect to board GND, which connects to host GND. Earth-referenced oscilloscope grounds and DUT grounds must be common — a DUT floating at an offset from host ground will pass current through the probe ground leads.
• The datasheet requires input transition rates of 10 ns/V or faster and the LVC245A has no Schmitt-trigger inputs: very slow or noisy DUT edges can cause output oscillation or multiple transitions, and an input held near threshold draws up to 500 µA extra supply current (ΔI_CC). This is a data-quality boundary, not a damage boundary.
• Standalone bench work uses a current-limited 3.3 V supply (limit ~50 mA; worst realistic dynamic draw is under ~20 mA, static under 0.5 mA).
• A clean capture of one known signal is not a timing certification; skew and bandwidth numbers below are calculated, and the module is unverified.

3. Power and control sequence#

There is no sequencing logic; the pod is combinational from power-up.

1. 3V3 and GND arrive on PMOD pins 6/12 and 5/11. C1 (100 nF) decouples U1 and C2 (1 µF) provides module bulk at the plug. The PMOD spec budgets roughly 100 mA per module — this pod uses a small fraction of it.
2. DIR (tied to GND) selects B-to-A propagation; ~OE (tied to GND) enables the A-port outputs. Both are hardwired: the pod has no control inputs.
3. With no probes attached, R1–R8 (100 kΩ) hold every PROBEx tip at GND, so every buffer input is at a legal static level (the datasheet requires unused inputs held at VCC or GND) and every CHx PMOD pin idles low.
4. Any level applied to a probe tip propagates through the 1 kΩ series resistor, the transceiver (t_pd ≤ 6.1 ns at 3.3 V, 25 °C), and the 100 Ω output resistor to the PMOD pin as a 3.3 V CMOS level.
5. Because I_off supports partial-power-down, a powered 5 V DUT connected to an unpowered pod leaks only ±1 µA typical into the inputs — a hot DUT does not back-power the pod.

4. Interfaces and pin maps#

All eight signal pins are module-driven (pod-to-host). The README and script label this "PMOD Type 1 (GPIO)"; in Digilent Pmod Interface Specification 1.2.0 the 12-pin 8-signal GPIO interface is formally Type 1A (Expanded GPIO) — Type 1 is the 6-pin variant. Functionally identical here, but the documentation should adopt the spec's name (discrepancy flagged in Section 12).

Per-channel resistor mapping (channel i = 0–7):

5. Component-by-component review#

Every reference designator in generate_design.py appears below. There are no DNP parts and no jumpers in this design. #FLG01 and #FLG02 are ERC power-flag pseudo-components on 3V3 and GND; they have no physical footprint and are listed only for completeness.

6. Datasheet summary and design interpretation#

Consulted: TI SN74LVC245A datasheet SCAS218X (January 1993 – revised January 2015), <https://www.ti.com/lit/ds/symlink/sn74lvc245a.pdf>, product page <https://www.ti.com/product/SN74LVC245A>; Digilent Pmod Interface Specification 1.2.0 (revised October 5, 2017), <https://digilent.com/reference/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf>. Both documents were fetched and read directly for this review.

Pmod Interface Specification 1.2.0 facts used: host supplies 3.3 V on pins 6/12 with GND on 5/11; module budget ~100 mA; signals are LVCMOS/LVTTL 3.3 V; standard host ports typically add their own 200 Ω series resistors and ESD diodes (in series with this pod's 100 Ω — harmless at FPGA input currents); the 12-pin 8-signal GPIO assignment is Type 1A. Check the latest revisions of both documents before procurement.

7. Expected values before bench testing#

Targets assume VCC = 3.300 V and 1% resistors. All are design targets, not measured results.

DC probe loading on the DUT. The tip network is 100 kΩ to GND in parallel with (1 kΩ + input leakage). Input leakage is ±1 µA typ (±5 µA at 85 °C), so the DC load is the pull-down: I = V/100 k = 33 µA at 3.3 V, 50 µA at 5 V per channel. A DUT source impedance R_s droops the high level by R_s/(R_s + 100 k): 1% (33 mV) at R_s = 1 kΩ — negligible for logic. Leakage through the 1 kΩ series resistor offsets the buffer input by at most 1 k × 5 µA = 5 mV.

Input RC bandwidth. The 1 kΩ series resistor drives the buffer input node: C_io = 5.5 pF plus an estimated ~2.5 pF pad/trace = ~8 pF, so τ = 1 k × 8 p = 8 ns, f−3dB = 1/(2πRC) = 1/(2π × 1 k × 8 p) ≈ 20 MHz, and 10–90% rise ≈ 2.2τ ≈ 18 ns. Probe-lead capacitance (~50–100 pF/m of flying lead) sits on the DUT side of the 1 kΩ and is charged by the DUT itself: a DUT with R_s = 100 Ω into a 50 pF lead adds τ ≈ 5 ns. The output side (100 Ω × ~10 pF FPGA pin + trace = 1 ns, ~160 MHz) is negligible.

Maximum capture rate. The pod is a buffer; the FPGA host is the sampler. The pod's silicon contributes t_pd ≤ 6.1 ns absolute delay (cancels within one pod) and t_sk(o) ≤ 1.5 ns channel-to-channel skew; the input RC adds ~18 ns rise plus a skew contribution from component tolerance (1% resistors, ±1 pF capacitance spread ≈ ±1 ns), so plan on ±2–3 ns channel-to-channel timing uncertainty. Fidelity is set by the ~20 MHz input pole: requiring a pulse to reach ≥ 90% amplitude means pulse widths ≥ ~2 × 18 ns ≈ 40 ns, i.e. signals with toggle rates up to roughly 10–12 MHz (square-wave fundamental) pass with clean levels; treat ~20 MHz as the hard fidelity ceiling. An FPGA sample clock of 100 MHz (10 ns resolution) comfortably oversamples everything the analog path can deliver; sampling faster than ~200 MHz buys nothing through this front end.

8. Manual schematic and assembly review checklist#

• Confirm U1 orientation (pin 1 = DIR at the pin-1 marker) and the PWR suffix (TSSOP-20/PW, 0.65 mm pitch).
• Verify DIR (pin 1) and ~OE (pin 19) both read 0 Ω to GND — a solder open on either leaves a floating control input and erratic behavior.
• Verify VCC (pin 20) to 3V3 and GND (pin 10) to GND.
• Per channel: buzz J2 pin (i+1) → 100 kΩ to GND, 1 kΩ to U1 B-pin (B1–B8 = pins 18 down to 11), and U1 A-pin (A1–A8 = pins 2–9) → 100 Ω → PMOD pin (CH0–CH3 = 1–4, CH4–CH7 = 7–10). Confirm no channel swap: the three-resistor chain and the PMOD pin must agree on the channel number.
• Confirm J2 pins 9 and 10 are grounds, not channels.
• Check C1 placement close to U1 pin 20 during layout review (layout not yet started — carry forward), and matched-length probe/channel routing if the ±3 ns skew budget matters to the lab exercises.
• Confirm no solder bridges on the 0.65 mm TSSOP, especially adjacent channel pins (a bridge shows as two channels always reading identically).
• Confirm the PMOD plug is the right-angle 2x06 male per Pmod spec 1.2.0 and that the pin-1 end matches the host port keying.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host identity, measured VCC, and the source equipment used for the known-signal tests.

Two bench contexts are used throughout: (a) PMOD host — plugged into a 3.3 V PMOD port on the ECP5 host (ULX3S-class), FPGA configured with all eight CHx pins as inputs (or left unconfigured for the early steps); (b) standalone — 3V3/GND wired from a current-limited bench supply (3.3 V, limit 50 mA) to PMOD pins 6/12 and 5/11, with a function generator on the probe tips and a scope on the CHx pins.

A. Unpowered inspection and resistance tests#

1. Complete the checklist above under magnification.
2. Measure 3V3-to-GND resistance in both polarities; investigate < 10 kΩ.
3. Walk all eight channels with an ohmmeter: 100 k tip-to-GND, 1 k tip-to-B-pin, 100 Ω A-pin-to-PMOD-pin (Section 7 table).
4. Confirm DIR and ~OE at 0 Ω to GND.

B. First power, no signals#

Standalone context (b) first: current limit 50 mA.

1. Supply current < 0.5 mA with all probes floating.
2. Every PROBEx tip and every CHx PMOD pin reads ~0 V (pull-downs working, no channel stuck high, no floating-input chatter on a scope).
3. Measure VCC at U1 pin 20.
4. Repeat the idle check in PMOD-host context (a) with the FPGA unconfigured, powered from the host port.

C. Static channel walk and the 5 V-tolerance check#

Standalone context. Drive one tip at a time from a bench supply through a DMM-verified source; scope or DMM the corresponding CHx pin.

1. 3.3 V walk. Apply 3.3 V to each tip in turn: that CHx reads ≥ 3.1 V, all other channels stay at 0 V (crosstalk/bridge check). Ground the tip: CHx ≤ 0.1 V.
2. 5 V tolerance (the design's central claim). Set the bench supply to 5.00 V with its current limit at 10 mA and apply it to one tip at VCC = 3.3 V:

• Source current ≈ 50 µA (the 100 k pull-down) — microamps, not milliamps, proving no input clamp to VCC is conducting.
• The CHx output reads ≥ 3.1 V — a 3.3 V CMOS high. It must never approach 5 V; 5 V on a CHx pin means a tip-to-output solder bridge and an FPGA-endangering fault. Stop immediately if seen.
• Supply current on the 3V3 rail stays in the static band (no ΔI_CC, since the input is above V_IH, not near threshold).
• Repeat on all eight channels. What is not demonstrated and must not be tried: tips above 5.5 V, negative supplies on tips, or driving the CHx outputs from outside.

1. Threshold walk. Sweep one tip 0 → 3.3 V slowly (supply, not a slow ramp generator — see the transition-rate caveat): the output must be low at 0.8 V and high at 2.0 V. Record the actual toggle point (typ ~1.5 V). Note that a 1.8 V "high" correctly fails to register.

D. Dynamic single-channel tests#

Standalone context, function generator (50 Ω source) on one tip, ≥ 200 MHz scope on tip and CHx pin.

1. 1 MHz square, 0–3.3 V: clean square out, t_pd ~4–10 ns, rise ~18–20 ns at the CHx pin (Section 7 math).
2. Walk frequency to 10 MHz and 20 MHz: expect visible edge rounding by 20 MHz (the 1 k × 8 pF pole) but full-amplitude levels through ~10 MHz. Record the frequency where the output no longer reaches 90% amplitude — this is the pod's measured fidelity ceiling versus the ~20 MHz estimate.
3. 0–5 V square at 1 MHz: output still swings 0–3.3 V (dynamic repeat of the tolerance check).
4. Same edge into two tips (power splitter or short stubs): skew between the two CHx pins ≤ ~3 ns; repeat across channel pairs.

E. Instrument validation against a known source#

This is an instrument board: before the pod is trusted to debug anything, it must reproduce signals whose truth is established independently of the pod. PMOD-host context (a), with the la_capture + sump_uart bitstream (once written) and PulseView connected over the UART; until that HDL exists, a minimal FPGA design routing CHx to SignalTap-style capture or even to LEDs/counters is an acceptable interim stand-in — record which was used.

1. Known-frequency square wave. Feed a calibrated generator (or a crystal-derived MCU clock output, frequency verified with a counter or scope first) at exactly 1.000 MHz into CH0. Capture at 100 MHz sample rate: period must read 1.000 µs ± 1 sample (10 ns), duty ~50%. Repeat at 100 kHz and 10 MHz.
2. Known UART. Feed 115200-baud UART (8N1) from a crystal-derived MCU or calibrated generator into CH1, with a known repeating byte (e.g. 0x55, which toggles every bit). Verify with a scope first that the source bit time is 8.68 µs. In the capture: bit time 8.68 µs ± 1 sample, and PulseView's UART decoder (or manual decode) recovers the exact byte stream. Repeat at 9600 baud.
3. Multi-channel coherence. Feed the same square wave into two channels and confirm the capture shows them edge-aligned within one sample.
4. Only after 1–3 pass may the pod be used on unknown signals; a capture disagreeing with its source by more than one sample interval is an instrument failure, not a DUT observation.

F. Host-integration and soak tests#

1. Probe a real 5 V DUT (e.g. a classic 5 V AVR SPI bus at ≤ 4 MHz) in PMOD-host context and verify a clean decode — the end-to-end use case.
2. All-channel burst: 8 channels toggling at 10 MHz; module supply current ≈ 15 mA estimate (Section 7), no capture corruption.
3. Hot-attach order checks: pod powered with hot 5 V DUT attached, and DUT hot with pod unpowered (I_off case) — both must be uneventful (< 10 µA leakage into the unpowered pod).
4. Long-lead susceptibility (1 m flying leads, noisy DUT) and temperature are out of scope for the first article; note the ESD story is HBM 2 kV plus 1 kΩ only.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design is a clean minimal buffer pod that puts its one important part-selection fact — LVC inputs accept 5.5 V regardless of VCC, verified here against SCAS218X — exactly where it belongs, and the three-resistor channel network is coherent: the 100 k pull-down satisfies the datasheet's unused-input rule and defines floating probes, the 1 k series resistor matches the negative-clamp current math, and the 100 Ω output resistors implement the lab line's module-driven rule while capping host-contention current. Direction and enable are hardwired to the only configuration the pod can meaningfully use, and everything in the README traces to the script except two items flagged here: the interface is formally PMOD Type 1A, not Type 1, in Digilent spec 1.2.0, and the PulseView/SUMP instrument claim depends on la_capture/sump_uart HDL that does not yet exist (the README own checklist concedes this). The principal open risks are that no PCB exists (layout, skew matching, and decoupling placement unverified), the J2 probe-header MPN is still TBD, the ~20 MHz input pole and ±3 ns skew budget are calculated rather than measured, ESD protection on human-handled probe tips is limited to the device's own HBM 2 kV rating plus 1 kΩ, inputs above 6.5 V or below −0.5 V remain genuinely destructive, 1.8 V logic is silently out of scope, and every number in this guide is derived from the datasheet rather than measured on hardware.