← usb-c-5v-breakout

Circuit review & bench-test guide

USB-C 5 V breakout

Document purpose#

This document is a component-level explanation and practical validation guide for the usb-c-5v-breakout prototype. It is intended to support manual schematic review, first power-up, fault investigation, and structured bench testing.

It describes the board as implemented in:

• usb-c-5v-breakout.kicad_sch
• usb-c-5v-breakout.kicad_pcb
• bom/qualified-bom.csv
• reports/qa-results.json

This is a prototype guide, not a certification report. Automated ERC, DRC, connectivity, analytical, and simplified simulation checks have passed, but hardware validation remains open. Record actual measurements rather than treating the calculated or simulated values in this document as acceptance evidence.

1. What the board does#

The board is a power-only USB Type-C sink. It:

1. presents the required Type-C sink pull-downs (Rd) on CC1 and CC2;
2. detects attachment and the source's Default, 1.5 A, or 3 A advertisement;
3. exposes that advertisement on two GPIO/status outputs;
4. accepts the source's initial 5 V VBUS;
5. protects and switches that 5 V through an eFuse; and
6. provides the protected rail on a screw terminal and an optional header.

It does not contain a USB Power Delivery controller. It cannot request 9 V, 12 V, 15 V, 20 V, or PPS. D+/D-, SBU1, and SBU2 are intentionally unconnected, so it also cannot enumerate as a USB device or transfer USB data.

Functional block diagram#

                         CC1 ───────────────┐
USB-C receptacle J1                       │
                         CC2 ───────────┐  │
                                       v  v
                                  +-------------+
VBUS_RAW ── R1 900 kΩ ───────────>| TUSB320LAI |── OUT1/OUT2 ── J4
    │                             | UFP, GPIO   |       │
    │                             +-------------+       └── status LEDs
    │                                    ^
    ├── D5 TVS ── GND                    │ VDD_5V
    ├── C1 4.7 µF ── GND                 │
    ├── D1 Schottky ─────────────────────┘
    │
    ├── UVLO/OVLO resistor dividers
    │
    v
+----------------+
| TPS259470A U2  |── FLT ── fault LED
| protected      |
| eFuse path     |── VOUT_5V ── C5 ── J2 screw terminal
+----------------+                  └── J3 light-load header

2. Important boundaries and safety notes#

• Use only a SELV, current-limited bench supply or a known-compliant USB-C source during ordinary bench work.
• The board is nominally low voltage, but a hard short can create high local temperature, damaged copper, molten solder, or connector damage.
• Do not test 3 A through a solderless breadboard. Use J2, appropriately sized wire, and a suitably rated electronic load.
• Never attach an earth-referenced oscilloscope ground clip to CC1, CC2, VBUS_RAW, or VOUT_5V. Connect it only to board GND. Use a differential probe for floating or high-side measurements and a current probe or appropriate shunt/differential setup for current.
• Remove the USB cable before applying an external voltage to TP1, TP2, J2, or J3. Do not connect two uncontrolled sources together.
• Do not perform IEC ESD, surge, or destructive short-to-VBUS tests on an open bench. Those tests require the correct generator, coupling network, probes, enclosure, fire controls, and trained personnel.
• J4 pin 1 (VDD_5V) is a board-generated logic/status rail, not a regulated 5 V auxiliary power output. Use it only for high-impedance sensing unless a separate load-budget review is completed.

3. Named nets and external interfaces#

Physical implementation relevant to circuit review#

• Board outline: approximately 55 mm × 50 mm, 1.6 mm finished thickness.
• Stackup: four copper layers (F.Cu, In1.Cu, In2.Cu, and B.Cu).
• The high-current route uses the paralleled J1 VBUS contacts, wider copper corridors, and J2 as the intended load interface.
• Unavoidable neck-downs exist at J1's fine contacts and U2's 2 mm QFN IN/OUT pads. These are priority points for voltage-drop and thermal measurements.
• Ground return and connector shell areas use multiple stitching vias. A good electrical schematic cannot compensate for missing/voided ground connections or poor QFN pad soldering.
• H1, H2, and H3 are 2.5 mm non-plated mounting holes. Ensure mounting hardware cannot touch copper, distort the PCB, or create an unintended chassis bond.

Connectors and test points#

4. How attachment and startup work#

4.1 Unpowered/dead-battery state#

Before VBUS exists, U1's dead-battery behavior presents approximately 5.1 kΩ Rd pull-downs on CC1 and CC2. A Type-C source detects Rd, determines that the board is a sink, and is then permitted to apply the initial 5 V VBUS.

If U1 or its CC connections are absent, a standards-compliant USB-C source may never enable VBUS. This is why a Type-C receptacle with only VBUS and GND wired is not a complete Type-C sink implementation.

4.2 U1 powers and resolves attachment#

VBUS_RAW feeds U1 through D1. On this board:

• U1 pin 3 (PORT) is tied to GND, selecting UFP/sink mode;
• U1 pin 5 (ADDR) is unconnected, selecting GPIO rather than I2C mode;
• U1 pin 11 (EN_N) is tied to GND, enabling the LA variant;
• CC1 and CC2 remain separate; and
• R1 routes VBUS_RAW to VBUS_DET through the required 900 kΩ resistance.

U1 waits for valid CC detection and VBUS detection, debounces the result, then reports the source's Type-C current advertisement on OUT1 and OUT2.

4.3 The eFuse enables the protected output#

At the same time, U2 receives VBUS_RAW. Its resistor dividers permit operation only when the input is above the configured UVLO point and below the configured OVLO point. C3 controls the initial output slew rate. C5 charges from the eFuse output, after which the load can draw from J2/J3.

The eFuse setting and the USB-C current advertisement are independent:

• U2 protects the board at approximately 3.4 A nominal.
• U1 only reports what the source permits.
• No circuit on this board automatically changes U2's current limit when the source advertises Default or 1.5 A.

Therefore, the downstream system or test operator must enforce the lower of:

1. 500 mA in the board's conservative Default-current case;
2. 1.5 A when medium current is detected;
3. 3.0 A when high current is detected; and
4. the actual load, cable, source, and thermal limits.

5. Type-C status decoding#

U1's OUT1 and OUT2 are open-drain outputs. R2 and R3 pull them high. The LEDs are connected from VDD through their series resistors to the outputs, so an LED turns on when its output is low.

At approximately 4.7 V VDD and about 2 V LED forward voltage, each active LED branch draws roughly (4.7 V - 2.0 V) / 3.3 kΩ = 0.82 mA, plus approximately 0.10 mA through its 47 kΩ pull-up. This is below U1's 1.6 mA characterized open-drain test current.

6. Component-by-component circuit review#

The failure descriptions below distinguish omitted/open failures from shorted failures because they often produce very different symptoms.

6.1 J1 — GCT USB4105-GF-A-120 Type-C receptacle#

Function: Provides the mechanical/electrical USB-C interface. All four VBUS contacts join VBUS_RAW; all four ground contacts join GND; A5 and B5 route independently as CC1 and CC2. D+/D- and SBU are unconnected.

Why it is needed: It provides a reversible Type-C connection with the correct contact sequencing and mechanical shell retention.

If absent/open: There is no source connection. An open CC contact can make one plug orientation fail while the other works. An open VBUS or GND contact increases resistance and heating; because contacts are paralleled, a partial solder defect can pass a light-load test but overheat at 3 A.

If shorted/mis-soldered: A CC-to-VBUS bridge can destroy U1. A VBUS-to-GND bridge can trip or damage the source. Shorting CC1 to CC2 breaks orientation detection and violates the Type-C connection model.

Review/bench focus: Microscope inspection of the fine signal pads, shell stakes, locating pegs, and all VBUS/GND pads; continuity in both orientations; temperature rise at 3 A.

6.2 U1 — TI TUSB320LAI Type-C CC controller#

Function: Implements the Type-C CC state machine, internal Rd, attachment detection, VBUS detection, and Default/1.5 A/3 A current-mode reporting.

Why it is needed: A passive VBUS breakout cannot correctly detect current advertisement or provide the intended status interface. U1 also avoids relying on two discrete Rd resistors with no attachment/current decoder.

Implemented pin configuration:

If absent/open: A compliant Type-C source may not enable VBUS because the sink pull-downs are missing. Status outputs are invalid.

Common partial failures:

• open CC1 or CC2: one plug orientation fails;
• open R1/VBUS_DET path: CC voltage can appear plausible, but U1 does not complete attachment;
• open VDD or GND: dead-battery Rd behavior may exist, but normal status does not operate correctly;
• bridged ADDR pin: U1 may enter I2C mode, making OUT1/OUT2 behavior inconsistent with the expected GPIO truth table;
• CC overvoltage/ESD damage: intermittent attach, wrong current decode, or orientation-specific failure.

6.3 R1 — 900 kΩ, 1% VBUS_DET resistor#

Function: Connects VBUS_RAW to U1's VBUS_DET input while limiting input current and forming the datasheet-defined detector network with U1's internal resistance.

Why it is needed: U1 requires VBUS confirmation to complete UFP attach. The high resistance allows sensing a 5–28 V system VBUS without applying that full voltage directly to the low-voltage internal detector node.

If absent/open: U1 may remain unattached or fail to update OUT1/OUT2 even though 5 V is physically present.

If shorted or wrong by orders of magnitude: VBUS can exceed the 4 V absolute maximum of the VBUS_DET pin and damage U1. Do not replace this with a 0 Ω link during debug.

Bench focus: Verify approximately 900 kΩ out of circuit or with one end lifted if an in-circuit reading is ambiguous. Do not load VBUS_DET with a low-impedance probe.

6.4 D1 — Nexperia BAT54H Schottky diode#

Function: Feeds VDD_5V from VBUS_RAW with a small forward drop and blocks reverse flow from VDD_5V toward raw VBUS.

Why it is needed: It isolates U1 and the status rail from the connector-side rail, particularly if J4 is connected to external logic or VDD remains charged. Its forward drop also provides modest voltage margin at nominal 5 V.

If absent/open: U1 and all three indicator/pull-up networks lose power. VBUS may still pass through U2 to VOUT, so the board can appear to deliver power while Type-C status is dead or invalid.

If shorted: U1 VDD is directly connected to raw VBUS. Normal 5 V operation may still work, but reverse isolation and the Schottky voltage margin disappear.

If installed backward: VDD_5V will not power normally. D1 pin 2/anode is on VBUS_RAW; pin 1/cathode is on VDD_5V.

Key ratings: 30 V reverse voltage, 200 mA forward current, and no more than 400 mV forward drop at 10 mA under the datasheet's pulsed test condition. The board normally needs only a few milliamps, but J4 must not be used to consume the diode's entire rating.

Supply-margin review finding: A Schottky diode is not a voltage regulator. Its forward drop becomes smaller at the approximately 70 µA U1-only load than at the datasheet's 10 mA test point. At the USB 5.25 V high limit with the LEDs off, verify that VDD_5V remains at or below U1's 5.0 V recommended maximum. U1's 6 V absolute maximum is a damage boundary, not a normal design target. If the measured/reviewed margin is inadequate, use a regulated or clamped U1 supply rather than relying on an assumed D1 forward drop.

6.5 C2 — 100 nF, 10 V X7R U1 bypass capacitor#

Function: Provides local high-frequency current and suppresses noise on U1's VDD pin.

Why it is needed: D1 and the VDD routing have impedance. U1 needs a local charge reservoir during internal switching and CC-state changes.

If absent/open: The board may work on a clean bench supply but become susceptible to false attach/detach, status glitches, or ESD-induced resets.

If shorted: VDD_5V is shorted to GND through D1, likely pulling down or heating D1 and loading the USB source.

Bench focus: Check for a solid ground connection and short placement near U1. A cracked MLCC can fail short after board flex.

6.6 R2/R3 — 47 kΩ OUT1/OUT2 pull-ups#

Function: Convert U1's open-drain OUT1 and OUT2 signals into defined high logic levels referenced to VDD_5V.

Why they are needed: Open-drain outputs can pull low but cannot generate a high level. Without pull-ups the unattached/default distinctions are undefined for an external logic input.

If absent/open: The corresponding output may float high only through the LED path or probe leakage. Logic readings become unreliable even if the LED appears to work.

If shorted: A direct VDD-to-output connection can overstress U1 whenever it tries to pull low.

6.7 R4/D2 and R5/D3 — amber status LED branches#

Function: Provide a visible active-low indication for OUT1 and OUT2. R4/R5 limit LED and U1 sink current; D2/D3 provide the light output.

Why they are needed: They allow current-mode observation without external instrumentation. They are not required for the underlying Type-C function.

If the entire branch is absent/open: Logic at J4 still works through R2/R3, but the corresponding LED never illuminates.

If an LED is shorted: The 3.3 kΩ resistor still limits current to roughly 1.4 mA, so U1 should remain protected, but the visual indication is lost and the low-state sink current increases.

If R4/R5 is shorted or wrong-low: U1 can be forced to sink excessive LED current and may be damaged. Do not bypass the series resistor.

6.8 D5 — Littelfuse SMAJ5.0CA bidirectional TVS#

Function: Shunts connector-side positive or negative transients from VBUS_RAW to GND.

Why it is needed: Cable inductance, hot-plug ringing, ESD coupling, or an abnormal source can create a voltage much higher than the steady 5 V rail.

If absent/open: Ordinary steady operation may be unchanged, but U2, D1, U1, and C1 receive the full transient. Immunity and fault survival decrease.

If shorted: VBUS_RAW is shorted to GND and the USB source should current limit or shut down. A TVS can fail short after absorbing energy beyond its rating.

Key ratings: 5.0 V stand-off, 6.4–7.0 V breakdown at 10 mA, and 9.2 V maximum clamp at 43.5 A for the specified pulse, with a 400 W 10/1000 µs series rating.

6.9 C1 — 4.7 µF, 50 V X7R input capacitor#

Function: Stabilizes VBUS_RAW locally and supplies high-frequency/transient current to U1 and U2.

Why it is needed: It reduces local rail collapse and ringing after the connector/cable impedance. Its value is chosen to retain useful capacitance under DC bias while staying below the board's 10 µF Type-C sink target.

If absent/open: Hot-plug peak current decreases, but raw VBUS becomes more sensitive to cable inductance, load steps, and TVS/eFuse switching. U1 or U2 may reset or chatter in marginal conditions.

If shorted: VBUS_RAW is shorted to GND. MLCC flex cracks are a relevant failure mechanism.

Key ratings/qualification point: 4.7 µF ±10%, 50 Vdc, X7R, 1206, -55 to 125 °C. The board calculation requires at least 27.8% of nominal capacitance to remain at 5.25 V after tolerance and the X7R temperature corner. Murata's published curve is typical rather than a production guarantee; retain an approval sheet or lot-qualified evidence for production.

6.10 U2 — TI TPS259470A eFuse#

Function: The main protected power switch. The selected 470A variant has:

• adjustable UVLO and OVLO;
• active current limiting;
• adjustable overcurrent blanking;
• controlled output slew/inrush;
• active-low fault output;
• thermal shutdown;
• integrated back-to-back FETs and true reverse-current blocking; and
• automatic retry after eligible fault/thermal recovery conditions.

Why it is needed: A direct connector-to-output connection would provide no controlled startup, programmable brownout/overvoltage cutoff, active current limit, reverse-backfeed block, or fault reporting.

Implemented pin configuration:

If absent/open IN-to-OUT: No protected output, even though U1 status may operate normally from raw VBUS.

If its power FETs fail short: VOUT follows raw VBUS with no eFuse cutoff; reverse blocking, current limit, UVLO/OVLO, and controlled slew are lost. This is why system safety must not assume a single semiconductor failure is always open-circuit.

If its ground pad is poorly soldered: Thresholds, current limit, fault behavior, and thermal performance can all be wrong. The 2 mm QFN/HotRod package requires careful paste, reflow, and inspection.

Key ratings: 2.7–23 V recommended input, 28 V absolute maximum, about 28.3 mΩ typical on-resistance, -40 to 125 °C characterized junction range, 0.5–6 A adjustable current limit, 500 ns typical fast-trip response, and approximately 110 ms auto-retry interval for A variants. Board-level thermal and safe-operating-area verification remains mandatory.

6.11 R6/R7 — 215 kΩ / 100 kΩ UVLO divider#

Function: Programs U2's rising undervoltage threshold.

VUVLO ≈ 1.2 V × (1 + 215 kΩ / 100 kΩ) = 3.78 V nominal
Calculated component/datasheet corner: 3.676 V to 3.906 V

Why they are needed: They prevent an undervoltage or severely collapsed USB rail from partially turning on U2 and dissipating excessive power.

If R6 is open: EN/UVLO is pulled low by R7; U2 remains off.

If R7 is open: EN/UVLO rises toward VBUS; the programmed UVLO protection is lost and the pin may be overstressed depending on conditions.

If R6 is shorted: EN/UVLO sees near-raw VBUS, outside its normal pin range.

If R7 is shorted: U2 remains disabled.

6.12 R8/R9 — 374 kΩ / 100 kΩ OVLO divider#

Function: Programs U2's rising overvoltage cutoff.

VOVLO ≈ 1.2 V × (1 + 374 kΩ / 100 kΩ) = 5.688 V nominal
Calculated component/datasheet corner: 5.520 V to 5.889 V

Why they are needed: Normal USB 5 V may reach 5.25 V. The divider places the cutoff above that expected maximum while disconnecting sustained higher input voltages before they reach VOUT.

If R8 is open: R9 pulls OVLO low, so sustained overvoltage cutoff is lost.

If R9 is open: OVLO rises and U2 may remain off or the pin may be overstressed.

If R8 is shorted: OVLO sees near-raw VBUS and U2 should turn off, but the pin can be overstressed.

If R9 is shorted: OVLO protection is disabled because the sense node is held low.

6.13 R10 — 976 Ω, 1% current-limit resistor#

Function: Programs U2's active current limit through the ILM pin.

Using the current datasheet characterization and resistor tolerance, the board QA estimates:

Why it is needed: The ILM pin must not float. R10 defines the board's main overload protection threshold while leaving tolerance margin for a legitimate 3 A load.

If absent/open: The datasheet states that an open ILM sets the current limit near zero, so even a small load can cause limiting/shutdown behavior.

If shorted: U2 detects an ILM-pin short as a fault and shuts down after its specified behavior; do not use a short as a way to request a larger limit.

If a lower resistance is fitted: The current limit rises, potentially above the USB-C 3 A entitlement and the board's validated thermal capability.

6.14 C3 — 330 pF, 50 V C0G dVdt capacitor#

Function: Programs U2 output slew and therefore capacitive inrush.

The datasheet relationship is approximately:

CdVdt(pF) = 2000 / slew-rate(V/ms)
slew rate ≈ 2000 / 330 = 6.06 V/ms
idealized 0-to-5 V ramp ≈ 0.83 ms
idealized C5 charging current ≈ 10 µF × 6.06 V/ms ≈ 61 mA

Load current is additional to this capacitor-charging current.

Why it is needed: An uncontrolled fast turn-on can produce high inrush and source reset; an excessively slow turn-on can leave U2 in its linear region too long and overheat it, especially with a pre-connected load.

If absent/open: U2 uses its fastest output slew. Inrush and ringing increase.

If shorted: The dVdt pin cannot charge normally and startup can be prevented or severely disturbed.

Why C0G: Its capacitance is stable with voltage and temperature compared with a high-K dielectric, making ramp timing more predictable.

6.15 C4 — 2.2 nF, 50 V C0G ITIMER capacitor#

Function: Sets how long an overcurrent above ILIM but below the fast-trip threshold may persist before active limiting behavior engages.

tITIMER ≈ C × ΔV / discharge current
Typical ≈ 2.2 nF × 1.51 V / 1.8 µA = 1.846 ms
Calculated component/datasheet corner: 1.075 ms to 3.351 ms

Why it is needed: It tolerates brief load transients without immediately entering the steady fault response while still reacting to persistent overload.

If absent/open: The datasheet specifies the fastest overcurrent response. The board may nuisance-limit on short transients.

If shorted: Response is also near-minimum delay but with increased device current; TI does not recommend this operating mode.

If too large: A dangerous overload may persist longer and U2 can spend more time at high dissipation.

6.16 C5 — 10 µF, 10 V X7R output capacitor#

Function: Stabilizes VOUT_5V, supplies load-step current, and reduces output droop after the eFuse.

Why it is needed: The eFuse, cable, and source cannot respond instantly to a load transient. C5 provides local stored energy and a controlled eFuse startup load.

If absent/open: Startup capacitive inrush falls, but output impedance and load-step droop increase. Some loads may reset or oscillate.

If shorted: VOUT is shorted to GND. U2 should limit current, assert fault, and may cycle thermally/automatically; the source and board still experience stress until the fault is removed.

Qualification point: Effective capacitance at 5.25 V can be substantially lower than the nominal 10 µF for an 0805 X7R part. Use the exact-part DC-bias curve when correlating load-step and ramp measurements.

6.17 R11/R12/D4 — eFuse pull-up and red fault indication#

Function: R11 pulls the active-low FLT output high. R12 limits LED current. D4 lights red when U2 pulls EFUSE_FLT_N low.

Why they are needed: R11 creates a defined digital signal; R12/D4 make it visible. The eFuse's protection functions do not depend on the LED branch.

If R11 is absent/open: The fault node may still be biased through the LED branch, but it is not a clean logic signal.

If R12 or D4 is absent/open: Fault protection still works, but the red LED does not indicate it.

If R12 is shorted: U2's open-drain FLT pin may be forced to sink excessive LED current.

Interpretation caution: An auto-retry fault can make the red LED pulse or appear dim depending on duty cycle. Capture FLT and VOUT with the oscilloscope rather than relying only on visual observation.

6.18 J2 — Phoenix Contact 1715721 screw terminal#

Function: Main connection for VOUT_5V and GND during load and thermal tests.

Why it is needed: It provides a mechanically secure, low-resistance output interface suitable for properly sized test wiring.

If absent: VOUT remains available at J3/TP2, but there is no intended high-current field connection.

Key data: 5.08 mm pitch, 17.5 A nominal terminal rating, AWG 26–14 range, 7 mm strip length, and 0.5–0.6 N·m specified tightening torque. These connector ratings do not raise the board above its 3 A design target.

Bench focus: Support the terminal body while tightening; Phoenix Contact warns that its single solder pin per contact should not absorb the tightening torque. Inspect solder wetting and measure terminal temperature.

6.19 J3 — optional 2-pin 2.54 mm header#

Function: Convenient VOUT/GND access for light-load experiments.

Why it is optional: It is useful for instrumentation and prototypes but is not the preferred 3 A path. The proposed Würth header is nominally rated 3 A, but mating jumper wires and solderless breadboards often are not, and contact resistance makes the complete assembly unsuitable for a 3 A validation path.

If absent: No electrical function is lost; use J2 or TP2.

6.20 J4 — 4-pin logic/status header#

Function: Exposes VDD_5V, OUT1, OUT2, and GND to a logic analyzer, microcontroller, or fixture.

Why it is needed: It permits automated current-advertisement validation.

If absent: LEDs still provide local status; signals remain measurable on the board.

External-interface caution: OUT1/OUT2 are already pulled up to VDD_5V, which can approach the raw 5 V rail. Confirm the receiving logic is 5 V tolerant or add level shifting. Do not externally drive OUT1/OUT2 high or low.

6.21 R13 — 0 Ω connector-shell link#

Function: Bonds the USB-C metal shell directly to board GND in the default configuration.

Why it is needed: It provides a short discharge/return path and avoids a floating shell. The footprint also allows the grounding strategy to be changed after an EMC review.

If absent/open: The shell floats, which can worsen ESD behavior and radiated susceptibility. In some enclosure architectures a deliberate capacitive or chassis bond may be preferable, but that must be designed intentionally.

If shorted: That is the intended default condition. If system chassis and signal ground are meant to be isolated, the 0 Ω population must be revisited.

6.22 TP1–TP5 and H1–H3#

Function: TP1–TP5 provide repeatable instrument access. H1–H3 are 2.5 mm non-plated mechanical mounting holes.

If absent: The electrical circuit still functions, but probing and fixture repeatability degrade. Avoid using mounting hardware that can contact copper or create an unintended chassis-ground path.

7. Datasheet summary by BOM line#

VERIFIED means the critical identity was checked against current manufacturer information. PROVISIONAL means the proposed part has the intended nominal value/package, but the exact purchasing AVL, lifecycle, temperature, and assembly information must still be frozen before production.

Primary manufacturer references#

• TI TUSB320LAI datasheet, Rev. D
• TI TPS25947 datasheet, Rev. C
• GCT USB4105 product information and drawing
• Littelfuse SMAJ series datasheet
• Nexperia BAT54H datasheet
• Murata GRM31CR71H475KA12L product data
• Phoenix Contact 1715721 product data
• Würth WR-PHD 2.54 mm single-row header family

8. Expected analytical and simulated values#

The source of each number matters:

• Datasheet: manufacturer guaranteed or characterized information under stated conditions.
• Calculated: resistor/capacitor equations with stated tolerance corners.
• Simulated: simplified behavioral model, not silicon-accurate proof.
• Measured: required bench result from the actual assembly.

9. Recommended bench equipment#

Minimum useful setup:

• programmable 0–6 V bench supply with adjustable current limit;
• known USB-C source fixtures capable of Default, 1.5 A, and 3 A advertisement, or a characterized Type-C source analyzer;
• electronic load capable of controlled CC steps to at least 3.8 A;
• 4-wire DMM for low-resistance/drop measurements;
• oscilloscope with at least four channels for VBUS, VOUT, FLT, and status;
• differential voltage probe or safe high-side measurement arrangement;
• current probe, or a characterized low-value shunt plus differential probe;
• thermocouples or a calibrated thermal camera with emissivity controls;
• microscope and suitable QFN/connector inspection capability; and
• appropriately rated short, load, cable, wire, and terminal hardware.

Helpful additions include a USB-C protocol/current-mode analyzer, source/cable matrix, environmental chamber, and X-ray inspection for U1/U2.

10. Ordered bench-test procedure#

Use a new test record for each board serial number. Stop when a step fails; do not continue into higher-current or destructive testing until the cause is understood.

10.1 Stage A — visual and assembly inspection, unpowered#

1. Record PCB revision, serial number, assembler, date, and BOM variant.
2. Confirm J1 is the -120 stake variant and U2 marking/order code corresponds to TPS259470A, not the latch-off or circuit-breaker variant.
3. Inspect J1 signal pads, all VBUS/GND pads, and shell stakes.
4. Inspect U1 and U2 orientation, solder bridges, voiding indicators, and exposed/thermal pad wetting as far as the process permits.
5. Confirm diode and LED polarity. D5 is bidirectional and has no circuit polarity requirement.
6. Confirm R10 reads approximately 976 Ω and R1 approximately 900 kΩ when measured in a way that isolates parallel circuit paths.
7. Confirm C1/C5 package sizes and inspect MLCCs for cracks.
8. Verify J2 soldering and mechanically support it while tightening wires.

Initial resistance checks:

• VBUS_RAW-to-GND should not be a hard short. The two divider chains alone are (215 kΩ + 100 kΩ) || (374 kΩ + 100 kΩ) ≈ 189 kΩ, although D5 leakage, semiconductor paths, meter polarity, and capacitor charging can change the displayed value.
• VOUT_5V-to-GND should initially show C5 charging and should not settle near zero ohms.
• VBUS_RAW-to-VOUT_5V should not read as a simple copper short; U2 contains back-to-back FETs.
• J1 shell to GND should be near zero ohms with R13 populated.
• CC1-to-CC2 must not be shorted.

10.2 Stage B — raw power-path bring-up without USB-C#

This test separates the 5 V power circuit from Type-C attachment behavior.

1. Remove all USB cables and loads.
2. Connect a current-limited bench supply to TP1 (VBUS_RAW) and TP5 (GND).
3. Start at 0 V with a 100 mA current limit. If the supply enters current limit while charging C5, raise the limit only after confirming there is no fault.
4. Ramp slowly to 3.5 V. VOUT should remain off below the actual UVLO rising point.
5. Continue toward 4.0 V. Record the VBUS voltage at which VOUT turns on.
6. Set 5.0 V. Measure VBUS_RAW, VDD_5V, and VOUT_5V.
7. Briefly set VBUS_RAW to 5.25 V and record the maximum VDD_5V. Verify it does not exceed U1's 5.0 V recommended maximum; do not confuse the 6 V absolute maximum with an acceptable steady operating point.
8. Return to 5.0 V. Verify OUT1=High and OUT2=High because no CC source is attached; both amber LEDs should be off.
9. Verify FLT is high and the red LED is off after startup.
10. Check supply current and device temperature for unexpected rise.

Expected no-load relationships:

VDD_5V ≈ VBUS_RAW - D1 forward drop
VOUT_5V ≈ VBUS_RAW - small U2 forward/regulation drop
OUT1 ≈ OUT2 ≈ VDD_5V when unattached

If VOUT is absent but VDD/status work, concentrate on U2, R6/R7, R8/R9, R10, C3/C4, and U2 soldering. If VOUT exists but VDD/status do not, concentrate on D1, C2, U1, and the VDD route.

10.3 Stage C — USB-C attach and current advertisement#

Use characterized source fixtures. A charger label is not proof of the actual CC advertisement.

For each Default, 1.5 A, and 3 A fixture:

1. Set the electronic load to zero or a safe pre-load.
2. Attach the USB-C plug in orientation A.
3. Record VBUS_RAW, VDD_5V, VOUT_5V, OUT1, OUT2, and LED state.
4. Confirm the status truth table.
5. Detach, wait for all rails to discharge, reverse the plug, and repeat.
6. Observe CC1 and CC2 only with high-impedance probes. Exactly one CC channel should show the active Rp/Rd voltage for a normal cable orientation.
7. Capture attach debounce and look for repeated attach/detach oscillation.

Acceptance goals:

• both orientations behave identically except which CC pin is active;
• OUT1/OUT2 match the source advertisement;
• no persistent oscillation or source reset occurs; and
• the configured load never exceeds the decoded entitlement.

10.4 Stage D — progressive load and voltage-drop test#

For a confirmed 3 A source:

1. Connect the electronic load at J2 using short, suitably sized wires.
2. Record no-load VBUS and VOUT.
3. Step through 0.1 A, 0.5 A, 1.0 A, 1.5 A, 2.0 A, 2.5 A, and 3.0 A.
4. At each point record source voltage, TP1 voltage, TP2 voltage, J2 voltage, input/output current, FLT, and component temperatures.
5. Calculate the drop across cable/connector and the drop from TP1 to TP2.
6. Use a four-wire measurement where possible; ordinary lead resistance can dominate milliohm-level calculations.

Do not run the 1.5 A and Default fixtures above their decoded limits merely to test U2. Use raw bench injection for eFuse-limit characterization.

10.5 Stage E — load-step response#

1. Use the 3 A fixture or a 5 V bench injection with adequate current limit.
2. Configure the load for 0.1 A to 3.0 A steps.
3. Capture VBUS_RAW, VOUT_5V, current, and FLT.
4. Record minimum VOUT, settling time, ringing, and source reset behavior.
5. Repeat with cable-length/source-impedance corners and at least the exact production C5 population.

The behavioral model predicts about 4.268 V minimum for its assumptions; this is a correlation point, not a universal pass limit.

10.6 Stage F — UVLO and OVLO characterization#

Use TP1 injection with no USB source connected.

1. Start with a light, stable load such as 50–100 mA.
2. Sweep input upward slowly through 3–4.2 V and record the VOUT turn-on point.
3. Sweep downward and record turn-off; note hysteresis and chatter.
4. Return to 5.0 V.
5. Sweep upward through 5.2–6.0 V while observing VOUT, FLT, OVLO, and device temperature. Use a low current limit during initial characterization. This sweep can drive U1 VDD above its 5.0 V recommended maximum before U2 trips, because U1 is powered upstream of U2. Keep the dwell short, monitor VDD_5V, and do not proceed if the U1 supply margin has not already been reviewed. An U2-only characterization can instead use documented rework to isolate D1/U1 on a designated test assembly.
6. Record OVLO trip and recovery in both sweep directions.
7. Repeat at representative temperature/load corners if required.

Expected rising bands are 3.676–3.906 V for UVLO and 5.520–5.889 V for OVLO. Do not exceed component absolute maxima to find a threshold.

10.7 Stage G — startup/hot-plug and inrush#

1. Use a current probe or a characterized shunt/differential setup.
2. Capture connector-side VBUS, TP1, TP2, input current, and FLT.
3. Test zero-load and 3 A pre-load cases only after progressive testing passes.
4. Repeat with short/long and low/high-resistance cables.
5. Record raw plug-in pulse into C1 separately from U2 output-ramp current.
6. Confirm that the source does not reset and U2 remains within its SOA.

The simplified model predicts an approximately 10 A, very short raw-C1 plug-in peak under its assumed source/cable impedance. This is not a continuous current and must be validated with probe bandwidth and fixture parasitics documented.

10.8 Stage H — current limit, overload, and short response#

Begin with a controlled electronic-load ramp, not a wire short.

1. Inject 5 V at TP1 with a source safely capable of the planned test and with an independent current limit.
2. Ramp the load above 3 A while capturing input current, VOUT, FLT, and U2 temperature.
3. Record onset current, foldback behavior, ITIMER delay, and retry behavior.
4. Compare the measured onset with the calculated 3.013–3.757 A range.
5. Only after the controlled overload test passes, apply a characterized low resistance or electronic short pulse.
6. Limit repetition and cool-down time. Record whether U2 enters thermal shutdown and whether the A variant retries at approximately 110 ms intervals after eligible recovery conditions.

Never leave a hard short unattended. Active limiting can make U2 dissipate roughly VIN × I until foldback, timer, or thermal protection changes state.

10.9 Stage I — reverse-backfeed test#

1. Disconnect USB and ensure TP1 is not externally powered.
2. Apply 0 V to VOUT through J2 using a current-limited supply.
3. Ramp VOUT to 5.25 V with a conservative current limit.
4. Measure current flowing toward TP1 and the resulting VBUS_RAW voltage.
5. Observe VDD_5V, FLT, and device temperature.
6. Remove the backfeed source and confirm normal operation afterward.

Do not use the simulation's approximately 1 µA result as the acceptance limit. Use the TPS25947 datasheet limits under the actual voltage/temperature conditions and record instrument resolution/offset.

10.10 Stage J — 3 A thermal soak#

1. Use J2 and a confirmed 3 A advertisement/source path.
2. Attach thermocouples or prepare thermal-camera surfaces on J1, U2, J2, VBUS/VOUT neck-down copper, and relevant cable contacts.
3. Record ambient and initial temperature.
4. Run 3 A for at least 60 minutes or until thermal equilibrium criteria are met.
5. Record temperature at short intervals initially and longer intervals after stabilization.
6. Repeat at the highest intended ambient or use a justified derating method.
7. After cooling, repeat visual inspection and voltage-drop measurements to detect latent connector/solder damage.

The analytical U2-only estimate is about 0.254 W typical to 0.405 W maximum at 3 A. It does not include connector, via, track, terminal, or cable heating.

10.11 Stage K — transient and connector-immunity testing#

This is a specialist laboratory activity. Required open gates include:

• measuring VBUS_RAW and U2 IN during applicable surge/ESD events;
• measuring VDD_5V against U1's 6 V absolute maximum;
• ESD testing CC1 and CC2 in both orientations;
• CC1-to-VBUS and CC2-to-VBUS fault testing; and
• confirming safe recovery with no latent leakage or attach degradation.

The present board has no dedicated external IEC-rated CC protection device. U1's component-level HBM/CDM ratings are not a substitute for system-level IEC connector immunity.

11. Troubleshooting guide#

12. Test record template#

Copy this table into the board's test log for each assembly.

13. Current release status#

Automated preflight currently reports no ERC errors/warnings, no electrical or geometric DRC violations, no unconnected pads, and no schematic-to-PCB parity issues. One non-electrical local-footprint synchronization warning remains for U2; its land pattern and pin map were independently reviewed.

The design is not production-released or certified. At minimum, close these physical gates before an unattended/end-product release:

• attach/current decode for all three advertisements and both orientations;
• 3 A thermal soak;
• hot-plug/inrush and load-step behavior;
• overcurrent, short, foldback, timer, thermal, and retry behavior;
• reverse-backfeed behavior;
• UVLO/OVLO trip and recovery;
• VBUS and VDD transient stress;
• CC ESD and CC-to-VBUS immunity;
• assembly inspection for U1, U2, and J1; and
• applicable USB-C, EMC, safety, and environmental compliance evidence.