← robot-power-dist

Circuit review & bench-test guide

robot-power-dist — Robot power distribution board

Document purpose#

This document explains the robot-power-dist board at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py is authoritative for parts, reference designators, nets, and values), the README, and the ERC report in reports/.

This board has NEVER been fabricated. Its status is: schematic generated, ERC clean (0 errors / 0 warnings), netlist membership verified (27 nets / 149 pins). There is no PCB layout, no BOM order, no assembled unit, and no first-article bench result of any kind. Every number in this guide — gate thresholds, divider taps, calibration constants, LED currents, dissipation figures — is a design target to verify on the first assembled board, not a proven result. Several MPNs still carry TBD: / TBD-confirm: prefixes and must be pinned before ordering.

1. What the board does#

The board fans a robot battery rail (VBAT, 6.4–12.6 V, 2S/3S LiPo, arriving already fused and reverse-protected from battery-power-input/) out to four independently fused output channels, behind one master high-side gate. The gate is a parallel pair of DMP4015SSS P-MOSFETs whose only turn-on path is a series chain through a normally-closed e-stop loop AND a host enable — the default state, and the state with any wire cut or host unpowered, is OFF. Each channel carries a 1206 fuse, a 20 mΩ 2512 shunt, an INA226 high-side monitor on a shared I2C bus (addresses 0x40/0x41/0x44/0x45), and a green output-live LED. All four INA226 ALERT outputs are wire-OR'd on one open-drain line (PWR_ALERT_N). The 3.3 V telemetry domain is supplied by the host over Qwiic and is fully separate from the battery power path.

It is not a certified safety device: no redundancy, no monitored contacts, no rated stop category. The no-auto-relatch rule is a fabric/host contract, not a hardware feature.

Functional block diagram#

VBAT 6.4-12.6 V                     PGATE
J1 ────────────┬──────────────────────┐
               │ R1 100k (pull OFF)   │ common gate
               │ D1 BZT52C10 clamp    v
               └────────────────> Q1 ‖ Q2  (2x DMP4015SSS, high-side)
                                      │
   PGATE ─ R2 10k ─ J2 NC e-stop      v
            loop ─ Q3 2N7002 ─ GND  VDIST ──┬─ F1 ─ R4 20m ─► J3 CH1  U1 INA226 0x40
                     ▲                      ├─ F2 ─ R5 20m ─► J4 CH2  U2 INA226 0x41
                     EN (J9.1,              ├─ F3 ─ R6 20m ─► J5 CH3  U3 INA226 0x44
                     R3 10k pull-down)      └─ F4 ─ R7 20m ─► J6 CH4  U4 INA226 0x45
                                            │
                     R15/R16/R17 ───────────┘   per channel: green LED (R8-R11 + D2-D5)
                     GATE_STATUS divider
                                             telemetry: J7 Qwiic / J8 header / J9 control
                                             SDA/SCL (R12/R13 + JP1/JP2), PWR_ALERT_N (R14)

2. Safety and scope boundaries#

• This is a paper design. Do not trust any figure here until it is measured on a fabricated, inspected board. Do not connect real robot loads until phases A–D below pass.
• Use a current-limited bench supply (not a LiPo) for all first-power tests. A lithium battery can deliver hundreds of amps into an assembly fault; a bench supply set to 500 mA cannot.
• The board deliberately has no input fuse and no reverse protection — those live on battery-power-input/. If you bench it standalone, add an inline fuse and observe polarity at J1; reversed VBAT forward-biases the Q1/Q2 body diodes and energizes VDIST unprotected.
• The e-stop gating is safety-themed, not safety-rated. Never make a person's safety depend on it. It has one contactor-equivalent (the FET pair), no monitored contacts, and a purely combinational AND.
• The INA226 VS pins run from 3V3 only. Never jumper 3V3 to VBAT/VDIST: the INA226 supply absolute maximum is 6 V and a battery rail destroys all four monitors at once.
• Keep total load within the ~8 A combined master-gate budget and within the upstream battery-board fuse. The INA226 reading saturates at ~4.1 A per channel — saturation is not proof the current stopped rising.
• Ground-referenced scope probes go to board GND only. Shunt drops are high-side, millivolt-level signals; use the INA226 or a differential measurement, not a grounded probe across the shunt.
• Fuse-blow tests are end-of-plan destructive tests. Do them last, with eye protection, on one sacrificial channel first.

3. Power-control sequence#

1. With J1 powered but nothing else connected, R1 (100 kΩ) holds PGATE at VBAT, so V_SG = 0 and Q1/Q2 are off. VDIST is dead. R3 (10 kΩ) holds EN low, so an unpowered or unconfigured host also means OFF.
2. The host arrives on J7/J8 (3V3 + I2C) and J9 (EN, GATE_STATUS, PWR_ALERT_N). The four INA226s power up from 3V3 and are readable at 0x40/0x41/0x44/0x45 even while the gate is off (their supply is the telemetry rail, not VDIST).
3. Turn-on requires both: the NC e-stop loop across J2 closed (button healthy / wire link fitted) and EN driven high. Then Q3 (2N7002) conducts and the series chain PGATE → R2 (10 kΩ) → J2 loop → Q3 → GND pulls the common gate down.
4. R1/R2 form a 100k:10k divider, so V_SG ≈ 0.909·VBAT — about 5.8 V at 6.4 V input and an unclamped 11.5 V at 12.6 V, which D1 (BZT52C10) clamps to ≤ 10 V. The FET V_GS rating is ±20 V; the clamp adds margin, it is not survival-critical.
5. VDIST energizes and each channel conducts through its fuse and shunt to its terminal. Channel LEDs (D2–D5 via R8–R11) light. The GATE_STATUS divider (R15 39k / R16 10k, R17 100R series) reports VDIST·10/49 on J9.2 (≈ 2.57 V at 12.6 V).
6. Opening the loop (button hit, wire cut, connector fall-off) or dropping EN breaks the pull-down chain anywhere along it; R1 recharges the gate to the source and the pair turns off. The hardware is combinational and non-latching: if the loop recloses while EN is still high, power returns. The no-auto-relatch rule (latch a GATE_STATUS drop, require a deliberate EN toggle) is a host/fabric contract that must be tested at the system level, not on this board alone.

Master-gate truth table (to be verified row by row in phase C)#

Only row 1 is ON. Rows 2–4 must all measure OFF; row 2 with EN floating (host unplugged) is the R3 pull-down check and gets its own step.

4. Interfaces#

There are no dedicated test points in the rev 0.1 schematic; bench access is via the terminals, headers, and component pads (PGATE at R1/R2/D1 pads, EN at R3, ST_DIV at R15/R16). Consider adding TPs at layout time.

5. Component-by-component review#

5.1 Master gate and e-stop chain#

5.2 Gate status divider#

5.3 Distribution channels (×4 — CH1/CH2/CH3/CH4)#

5.4 Telemetry and host interface#

6. Datasheet summary and design interpretation#

Check the latest datasheet revision and exact orderable suffix before procurement; all TBD: MPNs must be pinned first.

INA226 calibration math for the 20 mΩ shunt (per channel)#

• Full-scale current: 81.92 mV / 20 mΩ = 4.096 A.
• Current_LSB = full scale / 2¹⁵ = 4.096 / 32768 = 125 µA/bit (a clean round choice; keep it).
• CAL = 0.00512 / (Current_LSB × R_shunt) = 0.00512 / (125 µA × 0.020 Ω) = 0.00512 / 2.5e-6 = 2048 = 0x0800. Write 0x0800 to register 0x05.
• Power_LSB = 25 × Current_LSB = 3.125 mW/bit.
• Example config (register 0x00): default 0x4127 = 1-sample average, 1.1 ms bus + 1.1 ms shunt conversion, continuous shunt+bus (~2.2 ms per update). For quieter readings use 0x4527 (16-sample average, ~35 ms per update).
• Sanity anchors: 1.000 A through the shunt → shunt register (0x01) reads 20 mV / 2.5 µV = 8000 = 0x1F40; current register (0x04) reads 1.000/125 µA = 8000 = 0x1F40 (with CAL = 0x0800 they match by construction). VDIST = 12.60 V → bus register (0x02) reads 12.6/1.25 mV = 10080 = 0x2760.
• Accuracy floor: shunt ±1% dominates; INA226 gain ≤ 0.1%, offset ±10 µV = ±0.5 mA. Expect DMM-vs-register agreement within ~1–2% after assembly.

7. Expected values before bench testing#

All values are calculated targets from an unfabricated schematic.

8. Manual schematic and assembly review checklist#

• Confirm Q1/Q2 orientation against the SO-8 pinout (1–3 S, 4 G, 5–8 D): sources to VBAT, drains to VDIST. A reversed FET conducts through its body diode regardless of gating.
• Confirm D1 polarity: cathode to VBAT, anode to PGATE. Reversed = board permanently OFF (a confusing failure).
• Verify Q3 pinout (SOT-23: G/S/D) — a rotated part can tie LOOP_B to GND permanently, deleting the EN term of the AND.
• Buzz the entire pull-down chain unpowered: PGATE pad → R2 → J2.1, J2.2 → Q3 drain. Confirm no path from PGATE to GND that bypasses J2 or Q3.
• Verify per-channel INA226 A0/A1 straps against the address map (U1 GND/GND, U2 GND/3V3, U3 3V3/GND, U4 3V3/3V3) — a swapped strap silently misattributes channels.
• Verify every U1–U4 VS pin connects to 3V3, never VDIST (abs max 6 V).
• Confirm IN+/IN− of each INA226 land across its own shunt with the correct polarity (IN+ on the fuse side, IN− on the terminal side) and that VBUS ties to the VOUTn side.
• Measure R4–R7 (20 mΩ) with a 4-wire ohmmeter or note that a 2-wire DMM cannot resolve them; at minimum confirm they are not open.
• Measure R1, R2, R3, R12–R17 values in-circuit before first power.
• Confirm JP1/JP2 are bridged (or deliberately cut) to match the host's pull-up plan.
• Confirm F1–F4 fitted ratings against the actual loads and that the sum respects the ~8 A gate budget and the upstream battery fuse.
• Note J7 vs J8 pin-order difference (GND/3V3 vs 3V3/GND) on the harness drawings.
• Confirm all TBD: MPNs were pinned to real orderable parts before the build, and record what was actually fitted.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record serial number, fitted MPNs, equipment IDs, ambient, and operator. Use a current-limited bench supply (≤ 500 mA limit) until phase D.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 checklist under magnification.
2. Measure VBAT-to-GND and VDIST-to-GND resistance in both polarities; investigate any hard short.
3. Verify J2 loop wiring: with the link/button fitted, J2.1–J2.2 reads ~0 Ω; with the button pressed, open.
4. Ohm the fuses: each F1–F4 end-to-end near 0 Ω; VDIST-to-VOUTn total should read fuse + 20 mΩ ≈ near 0 Ω on a 2-wire DMM.
5. Confirm SDA and SCL each read ≈ 4.7 kΩ to 3V3 (JP1/JP2 bridged), and PWR_ALERT_N ≈ 10 kΩ to 3V3.

B. Telemetry domain only (no VBAT)#

1. Connect the host 3V3/I2C via J7 (or a USB-I2C adapter). Do not connect VBAT yet.
2. Measure 3V3 current draw (four INA226s: low single-digit mA expected).
3. I2C scan: exactly 0x40, 0x41, 0x44, 0x45 must ACK. Any other address, or a missing one, means a strap or solder fault — fix before proceeding.
4. From each device read Manufacturer ID (0xFE = 0x5449) and Die ID (0xFF = 0x2260).
5. Write CAL = 0x0800 and config 0x4127 to each; read back. Bus and shunt registers should read ≈ 0 (no VBAT yet).

C. Master-gate truth table and e-stop behavior (current-limited supply)#

1. Bench supply on J1: 12.0 V, 200 mA limit. No loads on J3–J6. Loop link fitted, EN floating.
2. Row 2 (EN floating): VDIST must be ≈ 0 V (R3 holds EN low). Record any leakage.
3. Row 2 (EN driven low): tie EN to GND — VDIST still OFF.
4. Row 1: drive EN to 3.3 V. VDIST must jump to ≈ VBAT; all four channel LEDs light; GATE_STATUS reads ≈ VBAT·10/49 (2.45 V at 12.0 V). Measure V_SG: ≈ 9–10 V (clamped). Repeat at 6.4 V input: VDIST follows, V_SG ≈ 5.8 V unclamped, GATE_STATUS ≈ 1.31 V.
5. Row 3: with EN still high, open the loop (press the e-stop / pull the link). VDIST must fall to ≈ 0. Scope PGATE and VDIST during the break and record the turn-off waveform.
6. Row 4: EN low and loop open — OFF.
7. Relatch check (design-intent confirmation): with EN held high, re-close the loop. Hardware will re-energize VDIST — this is the documented combinational behavior, not a fault. Confirm it, then verify the host/fabric supervisor (when present) latches the GATE_STATUS drop and refuses to re-enable without a deliberate EN toggle.
8. Repeat step 5 while GATE_STATUS is being sampled by the host: the drop must be visible fast enough for the supervisor contract (record latency).
9. Only after every row matches, raise the supply current limit for phase D.

D. Per-channel checks and calibration (known loads)#

1. One channel at a time: attach a known resistive load (e.g. 12 Ω/25 W for ~1 A at 12 V) to J3, with a DMM in series (or a calibrated shunt).
2. Gate ON: confirm VOUT1 ≈ VDIST minus microvolt-level shunt/fuse drops, LED lit.
3. Read U1 bus voltage, shunt voltage, current (with CAL = 0x0800), and power registers. Targets: current within ~1–2% of the DMM; bus within ~0.1%; power ≈ V×I with 3.125 mW LSB.
4. Compute the per-channel correction factor (DMM/register) and record it — this is the shunt-tolerance calibration named in the README.
5. Repeat for J4/U2, J5/U3, J6/U4. Confirm each reading appears at the expected address (load one channel at a time and check the other three read ≈ 0 A — this catches strap/attribution swaps).
6. Step one channel toward full scale (up to ~4 A briefly): confirm the reading saturates near 0x7FFF-equivalent (4.096 A) without damage and the fuse holds. Watch shunt temperature.
7. Load two channels simultaneously and verify the VBAT→VDIST drop and Q1/Q2 temperatures against the section 7 targets. A gross temperature imbalance between Q1 and Q2 means one FET is not conducting (solder or orientation).

E. Wire-OR ALERT test#

1. Idle state: PWR_ALERT_N (J9.3) reads 3.3 V with no alerts configured.
2. On U2 (0x41) only, configure Shunt-Over-Voltage alert: Mask/Enable register 0x06 = 0x8001 (SOL bit 15 + latch enable LEN bit 0) and Alert Limit register 0x07 = 0x0640 (1600 × 2.5 µV = 4 mV = 0.2 A threshold).
3. Apply a small ~0.3–0.5 A load to channel 2. PWR_ALERT_N must fall low.
4. Attribution: read Mask/Enable from all four devices. Only U2 must show AFF (Alert Function Flag, bit 4) set; the read clears the latched alert and the shared line must return high (remove the load first, or it re-asserts).
5. Repeat with the same load on channel 3 while U2's alert is still armed: the line must stay high (proves the alert is channel-specific and the wire-OR is not shorted between channels).
6. Arm two channels and load both: line low; both AFF flags set; line releases only after both are cleared/unloaded — confirms true open-drain wire-OR behavior on the single R14 pull-up.

F. Fuse and abuse tests (destructive, last)#

1. On one sacrificial channel with a spare fuse fitted, apply a supply- limited overload well above the fuse rating (e.g. 6–8 A from a supply into a 2 A fuse) and confirm the fuse opens, the channel dies, the LED goes dark, and the other channels are undisturbed. Note the INA226 will have saturated at 4.1 A during the event.
2. Verify post-blow: bus voltage register for that channel reads ≈ 0, no damage to the shunt or INA226 inputs.
3. Only after everything above: repeat selected phase C/D checks from the real battery-power-input/ chain instead of the bench supply.

G. Release-only tests#

System-level supervisor (no-auto-relatch fabric contract), vibration on the screw terminals, thermal soak at full budget in the enclosure, and the layout-dependent items (Kelvin shunt routing verification, copper heating) can only be assessed after a PCB layout exists — none does today.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The architecture is coherent and deliberately conservative: a default-OFF high-side gate whose only turn-on path is a series AND of an NC e-stop loop and a host enable, four channels that each carry their own fuse, shunt, and monitor, and a telemetry domain that cannot back-feed the power path. The design honestly documents its two sharpest edges — the combinational (non-latching) gate, whose no-auto-relatch guarantee lives in the host fabric, and the unmatched static current sharing of the parallel FET pair.

The principal risks are exactly what an unfabricated board implies: nothing has ever been measured. The highest-value first-article checks are the truth table (especially proving VDIST cannot energize with the loop open — a Q1/Q2 drain-source short or a J2 solder bridge silently deletes the e-stop), the D1 clamp at 3S voltage, INA226 address attribution, the CAL = 0x0800 current readback against a DMM, and the wire-OR ALERT attribution flow. Before any of that, the TBD: MPNs must be pinned, a PCB layout produced (wide VBAT/VDIST copper, Kelvin-ish shunt routing), and the resulting board built and inspected. Until then, treat every number in this guide as a target, and never as evidence.