← battery-power-input

Circuit review & bench-test guide

battery-power-input — AruviX robot battery power board

Document purpose#

This document explains the battery-power-input board at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the authoritative generator (generate_design.py), the project README, the ERC report, and the manufacturer datasheets cited in section 6.

This board has NEVER been fabricated. The design status is schematic capture only: ERC passes with 0 errors / 0 warnings (--severity-all, reports/erc.rpt) and the netlist membership was verified (23 nets / 123 pin memberships), but no PCB layout exists, no board has been ordered, and there is no first-article bench result of any kind. Every number in this document is a calculated design target to verify, not a proven result. Several MPNs are still marked TBD-confirm in the generator (fuse, 22 µF bulk capacitors, shunt) and must be resolved before ordering.

1. What the board does#

The board is the robot power foundation: a 2S or 3S hobby LiPo pack (6.4–12.6 V) enters on a screw terminal, passes a 5 A fuse, a reverse-polarity ideal-diode P-FET, a 16 V TVS clamp, and a 10 mΩ INA226 current shunt, then fans out to three outputs: a raw metered battery rail (VBAT_OUT, for motor rails / robot-power-dist) and two independent 2 A synchronous bucks — AP63205WU (5 V) and AP63203WU (3.3 V). All battery telemetry (bus voltage, current, power, programmable alert) leaves the board on I2C at address 0x40 via a Qwiic connector and an optional pin header.

It is not a BMS: there is no cell-level monitoring, balancing, charge control, or hard low-voltage cutoff on the raw rail. The buck EN dividers implement a selectable 2S/3S input-UVLO floor for the logic rails only; VBAT_OUT stays live below that floor. Host software owns low-voltage policy via the INA226.

Functional block diagram#

2S/3S LiPo (XT60 pigtail)
        │
        v
J1 screw terminal ──> F1 5 A fuse ──> Q1 DMP4015SSS ──> VBAT_P
   1 BATT+  2 GND     (VBAT_FUSED)    ideal-diode P-FET    │
                                      D on battery side    ├── D1 SMBJ16A TVS
                                      S on load side       ├── C1,C2 2x22 µF + C3 100 nF
                                      gate: R2 100k to GND ├── R6/R7(+R8,JP3) UVLO div (5 V)
                                      D2 10 V VSG clamp    └── R9/R10(+R11,JP4) UVLO div (3V3)
        VBAT_P
          │
          v
   R1 10 mΩ shunt ── U1 INA226 (IN+ = VBAT_P, IN− = VBUS = VBAT_OUT)
          │              │  I2C 0x40, ALERT ── R3 10k pull-up
          v              └──> J5 Qwiic / J6 header (DNP), R4/R5 4.7k + JP1/JP2
       VBAT_OUT
          ├────────────> J2 raw motor rail (LIVE below UVLO)
          │
          ├──> U2 AP63205WU ── L1 4.7 µH ──> 5V_OUT ──> J3   (D3 green LED)
          │    C5/C6 in, C9 BST, C7/C8 out, EN from R6/R7 divider
          │
          └──> U3 AP63203WU ── L2 3.3 µH ──> 3V3_OUT ──> J4  (D4 green LED)
               C10/C11 in, C14 BST, C12/C13 out, EN from R9/R10 divider

2. Safety and scope boundaries#

2.1 LiPo pack safety — read before anything else#

Lithium-polymer packs store enough energy to start a fire, and unlike a lab supply they have no current limit: a shorted 3S hobby pack can deliver hundreds of amps until something burns or the pack vents. This board's protection (fuse, reverse FET, TVS) is unverified — treat it as absent until phase-by-phase bench results say otherwise.

• Never use a real pack for first power-up. Use a current-limited bench supply set to the pack voltage (e.g. 8.0 V / 0.2 A initially) wired to J1 in place of the battery. Only attach a real pack after phases A–D pass.
• Never charge a pack through this board. There is no charge path, balancing, or CC/CV control. Charging happens off-board on a balance charger, in a LiPo-safe bag or sand bucket, attended.
• Verify XT60 pigtail polarity before ever attaching a pack. With the pack disconnected, buzz the pigtail: XT60 female (battery side) — the contact next to the bevel/“+” mark must land on J1 pin 1 (BATT+), the square-side contact on J1 pin 2 (GND). Then, pack in hand, measure the pack connector with a DMM and confirm +6.4 to +12.6 V with red on the “+” contact before mating. A reversed pigtail is exactly the fault Q1 exists for — do not use Q1 as a substitute for checking.
• Pack condition checks: no puffing, no dented or wrinkled foil, no cell below 3.0 V (measure per-cell on the balance lead). Reject and safely dispose of damaged packs; do not "test" them on this board.
• Storage and handling: store packs at storage charge (~3.8 V/cell) in a fireproof container, away from the bench. Bring one pack to the bench at a time. Keep a class-D-capable extinguisher or a bucket of dry sand within reach; water does not stop a lithium fire.
• Work discipline with a live pack: remove rings/watches, insulate spare XT60 contacts, never leave a pack attached to the board unattended, and disconnect the pack (not just the load) when changing anything.
• 2S/3S selection matters: set JP3/JP4 for the pack you will use before power-up. Running a 3S pack against the 2S UVLO floor (5.96 V) will not hurt the electronics, but it lets the host discharge the pack far below the safe 3.0 V/cell floor — a pack-killing, potentially fire-adjacent condition on the raw rail either way, since VBAT_OUT has no UVLO at all.

2.2 General bench boundaries#

• The 5 A fuse F1 protects the wiring, not loads or the pack. A fault below 5 A can cook a component indefinitely without blowing it.
• VBAT_OUT (J2) is a direct, fused battery rail: treat it with the same respect as the pack terminals. Short it and you are shorting the pack until F1 opens.
• Connect an earth-referenced oscilloscope ground only to board GND. The shunt (R1) and Q1 drops are high-side measurements — use a differential probe or the INA226 itself, never two single-ended grounds.
• Do not back-feed 5V_OUT or 3V3_OUT from external supplies while the battery input is attached; the bucks are synchronous and can behave unexpectedly with reverse energy. The AP632xx does not sink current from the output but this is not a validated bidirectional boundary.
• This is a prototype for a hobby robot platform. Passing these bench tests is not EMC, safety, or environmental certification.

3. Power-control sequence#

1. With nothing attached, all nets are dead. Q1's gate is held to GND by R2 (100 kΩ), but with no battery there is no VGS and no channel.
2. Battery attaches at J1 (or the current-limited bench supply masquerading as it). Current flows J1 → F1 → Q1. Q1 is oriented as an ideal diode: drain to the battery (VBAT_FUSED), source to the load (VBAT_P), gate to GND. The body diode (anode = drain, cathode = source) conducts first, lifting VBAT_P to about VBAT − 0.7 V.
3. As soon as VBAT_P rises, VGS = −VBAT_P appears across gate–source (gate at 0 V via R2, source at VBAT_P). DMP4015SSS VGS(th) is −1.5 to −2.5 V, and RDS(on) is specified at −4.5 V and −10 V, so at 6.4 V minimum pack voltage the channel is fully enhanced and the diode drop collapses to I×RDS(on) (≤15 mΩ at −4.5 V drive). D2 (BZT52H-C10) clamps VSG to about 10 V so a 12.6 V 3S pack cannot approach the ±25 V VGS abs max; roughly 26 µA flows through D2/R2 at 12.6 V.
4. If the battery is reversed, the body diode is reverse-biased and VGS ≥ 0 keeps the channel off: no current flows, nothing downstream sees the negative voltage. This is the entire reverse-protection story — verify Q1's orientation before trusting it (section 9, phase A).
5. VBAT_P charges C1/C2/C3; D1 (SMBJ16A, 16 V standoff) sits across the rail and only conducts on surges above its 17.8 V minimum breakdown.
6. VBAT_P feeds the two UVLO dividers (R6/R7 and R9/R10, pre-shunt, so their ~21 µA each is unmetered) and the shunt R1. Everything downstream of R1 — J2 and both bucks — is metered by U1.
7. Each buck enables when its EN divider crosses 1.18 V (rising): 5.96 V battery threshold with JP3/JP4 open (2S), 9.00 V bridged (3S). The AP632xx runs a fixed internal 4 ms soft-start, then regulates at 1.1 MHz. Falling thresholds: 5.36 V (2S) / 8.20 V (3S).
8. D3 (green, via R12 1 kΩ) lights on 5V_OUT; D4 (green, via R13 470 Ω) lights on 3V3_OUT. The AP632xx WU parts have no power-good pin — the LEDs indicate voltage presence only, not regulation accuracy.
9. U1 (INA226) powers from 3V3_OUT, so telemetry is only alive once the 3.3 V buck is up — below the buck UVLO the board is unmetered even though VBAT_OUT is live. Host software must treat missing telemetry as an alarm, not as zero current.

4. Interfaces: connectors, test points, jumpers#

The schematic defines no dedicated test points; bench probing uses the connector screw terminals and the passives named below. Adding TPs on VBAT_FUSED, VBAT_P, EN_5V, EN_3V3, SW_5V, and SW_3V3 is a recommended layout action.

Useful probe nodes: J1 pin 1 (BATT_P), the F1 clip on the Q1 side (VBAT_FUSED), either C1/C2/C3 pad (VBAT_P), either side of R1 (VBAT_P / VBAT_OUT — this pair is the shunt-drop measurement), J2 pin 1 (VBAT_OUT), R7/R10 top (EN_5V / EN_3V3), L1/L2 pads (SW and output nodes).

5. Component-by-component review#

5.1 Input protection chain#

5.2 Telemetry (INA226 and I2C)#

5.3 5 V buck (AP63205WU)#

5.4 3.3 V buck (AP63203WU)#

6. Datasheet summary and design interpretation#

Check the latest datasheet revision and exact orderable suffix before procurement; the Diodes and Littelfuse links above resolve from a browser but reject some automated fetchers.

7. Expected values before bench testing#

All values are calculated from generate_design.py values and the cited datasheets. None has ever been measured on this design.

7.1 DC operating points#

7.2 UVLO thresholds — the math to verify on the bench#

Datasheet model (DS41326 Fig. 22 / Eq. 1–2, EN rising 1.18 V / falling 1.10 V, pull-up 1.5 µA off → 5.5 µA on), equivalent form:

V_ON  = (1.18 / (Rtop ∥ Rbot) − 1.5 µA) · Rtop
V_OFF = (1.10 / (Rtop ∥ Rbot) − 5.5 µA) · Rtop

2S (JP3/JP4 open): Rtop = 46.4 k, Rbot = 11.3 k, Rtop∥Rbot = 9.087 k

• V_ON = (129.9 µA − 1.5 µA) × 46.4 k = 5.96 V rising
• V_OFF = (121.1 µA − 5.5 µA) × 46.4 k = 5.36 V falling

3S (JP3/JP4 bridged): Rbot' = 11.3 k ∥ 18 k = 6.942 k, Rtop∥Rbot' = 6.039 k

• V_ON = (195.4 µA − 1.5 µA) × 46.4 k = 9.00 V rising
• V_OFF = (182.2 µA − 5.5 µA) × 46.4 k = 8.20 V falling

Tolerance note: 1 % resistors plus the 1.15–1.23 V EN threshold spread give roughly ±4 % on these numbers — expect ~5.7–6.2 V (2S ON) and ~8.6–9.4 V (3S ON). Log the exact values per board.

7.3 Buck ripple and dynamics#

7.4 INA226 configuration and calibration — worked register math#

Shunt R1 = 10 mΩ. Maximum expected current: 8.19 A (full shunt scale; the fuse limits to 5 A continuous).

Current_LSB = 8.19 A / 2^15 = 0.25 mA/bit          (Eq. 2, rounded value)
CAL = 0.00512 / (Current_LSB × R_shunt)
    = 0.00512 / (0.25e-3 × 0.010)
    = 2048 = 0x0800                                 (Eq. 1)
Power_LSB = 25 × Current_LSB = 6.25 mW/bit

Register program for bring-up (7-bit address 0x40; write = pointer byte then two data bytes MSB first):

Identity sanity checks before trusting data: register 0xFE reads 0x5449 ("TI"), 0xFF reads 0x2260. Until CAL is written, current (0x04) and power (0x03) read zero by design — bus and shunt registers work uncalibrated.

Worked example to cross-check on the bench (2.00 A load, 11.1 V pack):

Shunt reg 0x01: 20 mV / 2.5 µV  = 8000  = 0x1F40  (sign bit clear)
Bus reg   0x02: 11.08 V / 1.25 mV ≈ 8864 ≈ 0x22A0 (reads post-shunt: pack − 20 mV)
Current   0x04: 8000 × 2048 / 2048 = 8000 → 8000 × 0.25 mA = 2.000 A
Power     0x03: 8000 × 8864 / 20000 = 3546 → 3546 × 6.25 mW ≈ 22.2 W

Handy identity for this CAL choice: CAL = 2048 makes the current register numerically equal the shunt-voltage register, so current[A] = shunt_reg × 0.25 mA — any divergence between the two registers indicates a readback or math bug, not the analog front end. Cross-check current against a series DMM (expect agreement within ~1 % + offset; shunt tolerance 1 % dominates).

8. Manual schematic and assembly review checklist#

Schematic/layout review (before ordering):

• Confirm Q1 net assignment matches the ideal-diode orientation: pins 5–8 (drain) on VBAT_FUSED, pins 1–3 (source) on VBAT_P, pin 4 (gate) to D2/R2. The generator's SO-8 pin table must match the datasheet (1–3 S, 4 G, 5–8 D — verified against DS35416).
• Confirm D1 cathode (pin 1, marking bar) lands on VBAT_P, anode on GND.
• Confirm D2 cathode on VBAT_P (Q1 source), anode on Q1_GATE.
• Confirm INA226 IN+ on VBAT_P, IN− and VBUS on VBAT_OUT, A0 = A1 = GND.
• Confirm J5 pin order is Qwiic (GND, 3V3, SDA, SCL) against the JST-SH footprint pin 1 marker.
• Layout (when it exists): J1→F1→Q1→R1→J2 path sized for 5 A; kelvin connections from R1 pads to the INA226 inputs; buck hot loops (CIN–VIN–SW–GND) minimized; C5/C10 tight to U2/U3 VIN pins.
• Resolve TBD-confirm MPNs (F1 fuse, C1/C2/C7/C8/C12/C13 22 µF, R1 shunt) before BOM release.

Assembly inspection (per board, before any power):

• U2 is AP63205WU-7 and U3 is AP63203WU-7 — same package, different marking; a swap puts 5 V on the 3.3 V terminal. Verify markings under magnification.
• Q1 pin-1 dot orientation; D1/D2/D3/D4 polarity (diode cathode bars, LED cathode marks).
• R1 is the 10 mΩ 2512 (metal-strip parts often marked R010); verify it is not a 0.1 mΩ or 100 mΩ lookalike.
• JP1/JP2 bridged, JP3/JP4 as intended for the first pack (open = 2S).
• Fuse clips seated, correct 5 A fast fuse installed.
• Solder quality on the 2512 shunt, the 1210 capacitors, and both TSOT-26 parts; no bridges on the 0.5 mm-pitch VSSOP-10 (U1).

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record everything in the section 11 template. Phases A–F use a current-limited bench supply on J1, never a battery. A real pack appears only in phase G.

A. Unpowered inspection, resistance, and FET-orientation checks#

1. Complete the section 8 assembly checklist under magnification.
2. DMM resistance, both polarities: J1+ to GND, VBAT_P to GND, VBAT_OUT to GND, 5V_OUT to GND, 3V3_OUT to GND. Expect no hard shorts (capacitor charging ramps are normal; the UVLO dividers read ~57.7 k from VBAT_P to GND through each divider, ~29 k combined with both, in parallel with whatever the DMM sees of the buck inputs).
3. Q1 orientation verification (DMM diode mode, fuse installed):

• Red lead on J1 pin 1 (battery side → Q1 drain), black on VBAT_P (Q1 source): expect a body-diode reading of roughly 0.4–0.7 V (spec VSD 0.7 typ / 1.0 max at 1 A; DMM test currents read lower).
• Reversed leads (red on VBAT_P, black on J1 pin 1): expect OL / no conduction (channel off, body diode reverse-biased).
• Gate to GND: ~100 kΩ (R2).
• If both directions conduct or the forward direction reads near 0 Ω: suspect a shorted or backwards Q1 — do not power. If the battery→load direction reads OL: Q1 is backwards (body diode pointing at the battery); a board built this way has no reverse protection and additionally never powers up normally. A shorted D2 mimics a "never enhances" Q1 later — it cannot be caught in this static test, but shows up in step B4.

1. Verify JP3/JP4 state matches the intended pack (open = 2S for first bring-up).
2. I2C bus: SDA and SCL each read ~4.7 k to 3V3_OUT (JP1/JP2 bridged), no shorts to GND.

B. First power-up — current-limited supply masquerading as the battery#

1. Bench supply: 8.0 V, current limit 0.2 A, output off. Wire to J1 observing polarity. No loads on J2/J3/J4. DMM on 5V_OUT.
2. Enable the supply. Expect: input current settles well under 10 mA; both green LEDs light; no part warms.
3. Measure: 5V_OUT 4.95–5.05 V, 3V3_OUT 3.27–3.33 V, VBAT_P ≈ supply minus a few mV, VBAT_OUT ≈ VBAT_P (µA-level shunt drop).
4. Q1 enhancement check: measure J1+ → VBAT_P differential. Expect ≤ a few mV at this current. A reading near 0.5–0.7 V means Q1 is running on its body diode (gate circuit fault: R2 open, D2 shorted or reversed, or gate landed on the wrong pin) — stop and fix before any load testing, or Q1 will burn at amp-level currents.
5. Scope SW_5V (L1 input pad): expect clean 1.1 MHz-region switching or PFM bursts at this light load; no continuous ringing after edges.
6. Reverse-input tolerance check (supply, not pack): disable output, swap J1 wiring, set limit 0.5 A, enable briefly. Expect ~0 mA input current and 0 V on VBAT_P/5V/3V3. Restore correct wiring. (This proves the reverse-protection story at low energy; never perform this experiment with a battery.)

C. Telemetry bring-up (INA226)#

1. Connect the I2C host (3.3 V logic) to J5. Scan the bus: the device must ACK at 0x40 only.
2. Read 0xFE = 0x5449 and 0xFF = 0x2260; read 0x00 = 0x4127 after reset.
3. Write CAL = 0x0800 to 0x05 (section 7.4). Read back.
4. No-load sanity: bus register ≈ supply voltage (LSB 1.25 mV); shunt and current registers near zero (idle draw is below ~2 LSB of current).
5. Apply a known load on J2 (e.g. power resistor drawing ~1 A, supply limit raised to 1.5 A). Verify shunt reg ≈ current reg numerically (CAL = 2048 identity), current ≈ series-DMM reading within ~1–2 %, bus ≈ VBAT_OUT, power ≈ bus × current.
6. Alert check: write 0x06 = 0x1000 (BUL), 0x07 = 0x1540 (6.8 V). Lower the supply to 6.5 V: ALERT (J6 pin 5, populate J6 or probe R3) must go low; raise to 8 V: releases (transparent mode). Restore 0x06 = 0x0000.

D. Buck load, ripple, and efficiency#

Supply at 8.0 V (later repeat key points at 6.4, 7.4, 11.1, 12.6 V), limit 3 A. Electronic load on J3, then J4. Short, thick leads; sense at the terminal.

1. Load sweep (line/load regulation): at each input voltage, step the 5 V load through 0 / 0.1 / 0.5 / 1.0 / 1.5 / 2.0 A. Record J3 voltage (target: within 4.95–5.05 V in CCM plus small load regulation — record the actual curve; datasheet Fig. 6 shows ~1 % droop 0→2 A), input current, and U2/L1 temperature. Repeat for the 3.3 V rail at J4 (3.27–3.33 V window).
2. Output ripple (probe technique matters): 20 MHz bandwidth limit, tip-and-barrel (probe ground spring on the output-capacitor pad — no ground clip lead, which adds tens of mV of pickup at 1.1 MHz). Measure at C7/C8 (and C12/C13) at 2 A, 12.6 V in. Target < 20 mV pk-pk; calculated core value is only ~3–4 mV, so a 50+ mV reading means probe pickup, capacitor derating, or layout trouble — investigate before accepting.
3. Load step: 0.2 A → 2 A → 0.2 A steps (load slew ~1 A/µs), capture VOUT deviation and recovery on each rail. No datasheet limit exists; record the baseline (expect recovery within hundreds of µs, deviation well under ±150 mV). Watch for ringing that suggests marginal COUT.
4. Both rails loaded simultaneously (2 A + 2 A, input ≥7 V, limit raised accordingly): re-verify regulation and thermals. Total input power at 12.6 V should be roughly (10 W + 6.6 W)/η with η per datasheet Fig. 4 (~90 % region) — log efficiency.
5. Overload/hiccup: slowly raise one rail's load past 2 A. Expect cycle-by-cycle limiting somewhere in 2.5–3.1 A peak, then hiccup (repeating ~16 ms off bursts) on a hard short. Confirm recovery when the short is removed and that the other rail rides through (they share VBAT_OUT — record any coupling). Keep shorts brief on a hot board.
6. Thermal soak: 60 min at 2 A + 2 A, 12.6 V in, worst intended ambient. Log U2, U3, L1, L2, R1, Q1, F1 temperatures. TSOT-26 θJA is 89 °C/W — at roughly 0.5–0.7 W loss each buck may run 45–60 °C above ambient; investigate anything trending past ~110 °C junction estimate.

E. UVLO threshold verification — both jumper positions#

Do this with the bench supply (no pack) and light loads (~0.1 A per rail) so the thresholds aren't masked by droop.

1. 2S position (JP3/JP4 open):

• Sweep down slowly (≤0.1 V/s) from 8.0 V. Record where each rail drops out: expect 5.36 V falling (window ~5.1–5.6 V with tolerances). Note both rails independently — R6/R7 and R9/R10 are separate dividers and may differ slightly.
• Sweep up from 4.5 V. Record turn-on: expect 5.96 V rising (~5.7–6.2 V). Confirm hysteresis ≈ 0.6 V and that startup is clean (single 4 ms soft-start ramp, no chatter near threshold).

1. 3S position (bridge JP3 and JP4 with solder):

• Sweep down from 11.0 V: rails drop at 8.20 V falling (~7.9–8.5 V).
• Sweep up from 7.0 V: rails start at 9.00 V rising (~8.6–9.4 V).
• Verify VBAT_OUT (J2) tracks the supply throughout — the raw rail must NOT turn off at UVLO; only 5 V/3.3 V do.

1. Restore the jumpers to the configuration matching the first real pack and re-verify once.
2. Note for the record: below UVLO the INA226 loses its 3.3 V supply — confirm the host sees the bus NACK (0x40 disappears) rather than a zero-current reading. This is the "unmetered live motor rail" state the README warns about.

F. Input transient and DC robustness (still supply-fed)#

1. Hot-plug emulation: with 30–50 cm of typical silicone battery wire between supply and J1, snap the connection at 12.6 V and capture VBAT_P with single-shot trigger. Ring peak must stay below ~17 V (D1 breakdown floor); if D1 conducts on every plug, add bulk or revisit the clamp choice.
2. DC line sweep 6.4 → 12.6 V at 1 A + 1 A load: no dropouts, no LED flicker, monotonic INA226 bus readings.
3. Fuse path check: measure the total drop J1+ → J2+ at 5 A briefly (fuse + Q1 + shunt + copper). Expect on the order of 100–200 mV; the fuse element itself contributes tens of mV and warms — normal.

G. First real pack — only after A–F pass#

1. Pre-checks: pack per-cell voltages ≥3.6 V, no damage; pigtail polarity re-verified with DMM against J1 markings; JP3/JP4 match the pack; correct fuse installed; fire container at hand.
2. Attach the pack with no loads. Expect exactly the phase-B quiescent behavior. Verify INA226 bus reading matches the pack voltage.
3. Repeat one load point per rail (1 A) and one J2 load point, watching temperatures. Keep the first pack session under 10 minutes, attended.
4. Endurance and integration (motor rails, robot-power-dist, host low-voltage policy exercising ALERT) belong to the platform test plan, not this guide.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The architecture is a clean series protection chain (fuse → reverse FET → TVS/bulk → shunt) feeding one raw and two regulated rails, with the telemetry deliberately placed so the INA226 meters the entire robot. Its strongest design decisions are the electrically-correct ideal-diode orientation (drain-to-battery — a documented deviation from the original task pin, and the right call), datasheet-table buck components rather than guessed ones, and per-rail UVLO dividers with an explicit 2S/3S select.

The principal risks, in order: (1) nothing here has ever been built — no layout, no first article, so every number above is a target; (2) the board is not a BMS and the raw VBAT_OUT rail is live below UVLO and unmetered when the 3.3 V rail is down — host policy is a hard dependency for pack safety; (3) assembly-sensitive single points: Q1 orientation (reverse protection silently absent if backwards), the U2/U3 variant swap, and the 10 mΩ shunt value; (4) TBD-confirm MPNs (fuse, bulk 22 µF, shunt) must be locked before ordering; (5) hot-plug transient behavior and dual-rail overload coupling are analytically fine but only bench captures will close them. Follow the phase order in section 9 — in particular, the first thing this board ever meets must be a current-limited bench supply, not a LiPo pack.