← AXS-046

Circuit review & bench-test guide

AXS-046 — GPS/GNSS carrier PMOD module

Document purpose#

This document explains the axs-046-gps PMOD carrier at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on generate_design.py, README.md, and the ERC report in reports/.

This board has never been fabricated. Repository status is schematic generated, ERC clean (0 errors / 0 warnings), netlist reviewed; PCB layout not started; not released. There is no PCB, no BOM export, no DRC record, and no first-article bench result. Every number below is a target to verify against real hardware, not a proven result.

1. What the board does#

The board is a passive PMOD carrier for a 3.3 V UART GPS/GNSS breakout with PPS, intended to be an ATGM336H-class module (e.g. an ATGM336H-5N31 breakout, built on the AT6558 GNSS chip). The breakout plugs into a 1x5 socket; the carrier adds the Digilent PMOD Type 3 (UART) interface with the 1 Hz PPS signal riding in the pin-1 CTS position, series resistors on the two module-driven lines, and local decoupling. There is no active silicon on the carrier itself.

The FPGA host receives 9600-baud 8N1 NMEA sentences, parses them in fabric, and can discipline a fabric counter against the 1 Hz PPS edge.

Functional block diagram#

PMOD host (3.3 V)                Carrier                     Plug-in breakout
┌───────────────┐      ┌──────────────────────────┐       ┌─────────────────┐
│ J1 pin 1 PPS  │<─────│ PPS ──R2 100Ω── GPS_PPS <├───────│ PPS             │
│ J1 pin 2 TXD  ├─────>│ TXD ────────────────────>├──────>│ RX   ATGM336H-  │
│ J1 pin 3 RXD  │<─────│ RXD ──R1 100Ω── GPS_TX  <├───────│ TX   class GNSS │
│ 3V3 (6, 12)   ├─────>│ 3V3 ──┬──┬──────────────>├──────>│ VCC  breakout   │
│ GND (5, 11)   ├──────│ GND   C1  C2             ├───────│ GND  + antenna  │
└───────────────┘      │      100n 10µ            │  J2   └─────────────────┘
                       └──────────────────────────┘  1x5 socket

TXD/RXD are named from the host FPGA's viewpoint: host TXD → module RX, module TX → R1 → host RXD.

2. Safety and scope boundaries#

• Voltages are limited to 3.3 V, so electrical hazard is low. The real risks are module destruction from a mis-ordered breakout (section 9.B) and wasted hours from indoor fix attempts (section 7).
• GPS breakout pin orders vary between vendors — VCC/GND/TX/RX appear in different sequences and some boards add EN or BAT pins. Never insert a breakout without completing the pin-order verification in 9.B.
• Standalone bench work must use a current-limited 3.3 V bench supply (100 mA limit; the module draws ~25 mA at 3.3 V, more briefly during acquisition).
• The module supply range is 2.7–3.6 V. Never apply 5 V to a 3.3 V-only ATGM336H breakout unless that specific breakout documents an onboard regulator.
• GNSS reception indoors is unreliable: a module may never achieve a fix indoors. Do not diagnose the carrier as faulty from an indoor no-fix alone; NMEA output (which starts before any fix) is the electrical health signal.
• ERC-clean is a schematic check only. No PCB exists; layout, DRC, fabrication, and assembly quality are all unverified.

3. Signal and power sequence#

1. 3V3 and GND arrive from the PMOD host (pins 6/12 and 5/11) or the bench supply. C2 buffers acquisition-current peaks; C1 decouples the socket.
2. The module boots and, within roughly 1 s, begins transmitting NMEA sentences at 9600 baud 8N1 on GPS_TX — boot banners ($GPTXT) followed by $GNGGA, $GNRMC, etc. with empty position fields before a fix.
3. GPS_TX reaches the host RXD through R1 (100 Ω); the host UART receiver can be verified immediately, fix or no fix.
4. Host TXD → module RX is only needed to send configuration commands (e.g. CASIC/$PCAS sentences to change rate or baud); the module works with this line idle high or even disconnected.
5. After the module computes a position fix (GGA quality field 0 → 1, RMC status V → A), position fields populate and — module-firmware dependent — PPS begins pulsing once per second through R2 to PMOD pin 1.

4. Interfaces#

PMOD pin map (Type 3 UART, host viewpoint):

Note the non-standard use of the Type 3 CTS position for PPS: a generic PMOD UART host design that actively drives CTS would contend with the module's PPS output through R2 — the AruviX host gateware must treat pin 1 as an input.

There are no test points defined yet (no layout exists); bench probing is at J1/J2 pins and passives.

5. Component-by-component review#

5.1 Connectors#

5.2 Line conditioning#

Note there is deliberately no series resistor in the host-driven TXD → module RX path: the host drives it, the module only listens, and both are 3.3 V logic.

5.3 Decoupling#

#FLG01/#FLG02 are ERC power-flag symbols only — no physical parts.

5.4 The plug-in module (in scope)#

6. Datasheet summary and design interpretation#

Official references: ATGM336H-5N datasheet PDF (LCSC mirror), ATGM336H-5N31 at LCSC (C90770), example ATGM336H breakout (Tinytronics), Murata GRM188R71C104KA01D, Murata GRM21BR61A106KE19L, Yageo RC thick-film series. The ATGM336H datasheet is Chinese-language in places and the breakout board's own schematic (regulator? level shift? pin order?) is a separate document you must obtain for the specific breakout purchased.

7. Expected values before bench testing#

All values are design targets for a board that does not yet exist.

8. Manual schematic and assembly review checklist#

• Verify J1 odd/even pin numbering against the Digilent PMOD spec on the first layout: 3V3 on PMOD 6/12, GND on 5/11. A row swap is the most dangerous plausible layout error.
• Verify J2 net order on the physical board: 1 = 3V3, 2 = TXD, 3 = GPS_TX, 4 = GPS_PPS, 5 = GND. Buzz it before any module is inserted, and make sure the silkscreen labels each J2 pin by function, not just pin number.
• Confirm R1 and R2 are both 100 Ω in the GPS_TX→RXD and GPS_PPS→PPS paths and that the host-driven TXD line is direct.
• Confirm C1/C2 placement close to J2 in the eventual layout; keep the eventual antenna area clear per the README's 20 × 40 mm plan.
• Confirm host gateware treats PMOD pin 1 (CTS position) as an input.
• Confirm the eventual layout keeps switching noise away from the module's antenna area (GNSS signals are below thermal noise; this matters).

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, breakout identity (vendor, exact silkscreen), equipment, and location/sky view.

A. Unpowered inspection and resistance tests (no module fitted)#

1. Visual inspection under magnification: J1/J2, R1, R2, C1, C2; no bridges.
2. DMM: 3V3-to-GND high resistance both polarities; the three J1-to-J2 path measurements from section 7 (100 Ω / 100 Ω / 0 Ω); J2 pin 1 to J1 pin 6 ≈ 0 Ω; J2 pin 5 to J1 pin 5 ≈ 0 Ω.

B. Breakout pin-order verification (BEFORE first insertion — mandatory)#

GPS breakouts do not share a standard pin order. The same "ATGM336H breakout" is sold with VCC-first, GND-first, and TX/RX in either order; some add EN/BAT pins and become 1x6.

1. Buzz out the carrier socket with a DMM: identify which J2 position carries 3V3, GND, TXD, GPS_TX, GPS_PPS (per this design: 1/5/2/3/4 respectively). This is the carrier's ground truth from generate_design.py.
2. Read the breakout's own silkscreen pin by pin and, if available, its schematic. Map each breakout pin to the J2 position it will land in.
3. Every position must match by function: breakout VCC → J2 3V3, breakout GND → J2 GND, breakout TX → J2 GPS_TX, breakout RX → J2 TXD, breakout PPS → J2 GPS_PPS. A 1x6 breakout does not fit — do not force-offset it.
4. Consequences of getting this wrong: swapped VCC/GND is reverse polarity and can destroy the module instantly (most breakouts have no reverse protection). Swapped TX/RX is harmless — two outputs never fight here because R1 sits in one path and both are firmware inputs/ outputs at 3.3 V — the symptom is simply silence: no NMEA at the host.
5. If the pin order does not match, do not plug it in. Rework options are a header adapter or choosing a matching breakout — never "close enough".

C. Standalone module smoke test (bench supply, module alone)#

1. Power the bare breakout from a current-limited 3.3 V supply (100 mA limit). Confirm ~25 mA-class draw, no heating.
2. Attach a 3.3 V USB-UART or scope to the breakout's TX: NMEA sentences at 9600 8N1 must appear within ~1 s of power, fix or no fix.
3. Only a breakout that passes this goes into the carrier.

D. Standalone carrier bring-up (bench supply into J1 3V3/GND, no host)#

1. With the verified module fitted, feed the current-limited 3.3 V supply into J1 pin 6 (3V3) and pin 5 (GND). Confirm current as in C.1.
2. Scope J1 pin 3 (host RXD side of R1): 9600-baud NMEA bursts once per second, idle high at 3.3 V, clean edges.
3. Attach a 3.3 V USB-UART (RX to J1 pin 3, GND to GND) and log: expect $GPTXT boot text, then $GNGGA,,,,,,0,... / $GNRMC,...,V,... sentences with empty position fields — this proves the whole carrier signal path with zero sky view.
4. Move outdoors or to a window with sky view. Watch GGA quality go 0 → 1 and RMC V → A; record TTFF (expect ~30–35 s outdoors from cold, possibly minutes on the first-ever start; indoors may never fix).
5. Scope J1 pin 1 for PPS after fix: 1 pulse per second, ~3.3 V high level, record pulse width (commonly ~100 ms on this module class) and whether any pulses occurred before fix.
6. Optionally send a $PCAS rate/config command into J1 pin 2 from the USB-UART TX and confirm the module accepts it (proves the TXD path).

E. Hosted bring-up (PMOD host providing 3.3 V)#

1. Confirm the host gateware maps pin 1 as input before plugging in.
2. Plug the carrier into the FPGA PMOD port. Confirm the host 3.3 V rail is happy with the ~25 mA load (trivial for a real host, but record it).
3. Bring up the fabric UART RX at 9600 8N1 on RXD; verify received bytes match a parallel USB-UART tap character-for-character.
4. Run the NMEA parser: display fix quality, satellite count, time, and position. Repeat the TTFF observation from D.4 through the fabric path.
5. Discipline a fabric counter against PPS: measure the host-clock count between PPS edges over minutes; the spread is your oscillator error — this is the module's L3 lesson working end to end.
6. If configuration is implemented, exercise host-TXD commands (rate change) and confirm the effect, then return to defaults.

F. Robustness checks#

1. Power-cycle behavior: repeated cold/warm starts; record warm-start TTFF (seconds, thanks to retained ephemeris/RTC if the breakout has a backup battery — note whether it does).
2. Long PMOD cable (if used): re-verify UART edge quality and rail droop during acquisition.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The carrier is deliberately minimal and coherent for its L3 lesson: the two module-driven lines (GPS_TX, PPS) get 100 Ω of series protection, the host-driven line is direct, and C1/C2 handle acquisition current at the end of a PMOD cable. Placing PPS in the PMOD Type 3 CTS position is a pragmatic but non-standard choice that obligates the host gateware to treat pin 1 as an input. The design's single sharp edge is breakout variability: pin orders differ across vendors, and a reversed supply can destroy the module, so the 9.B verification procedure is mandatory, not advisory. The principal open risks are that no PCB exists yet (J1 row order, J2 order, and antenna-area layout are all unbuilt and unverified), PPS behavior (before-fix output, pulse width) is firmware-dependent and must be measured rather than assumed, and every figure in section 7 comes from datasheets and protocol definitions rather than a bench.