← AXS-040

Circuit review & bench-test guide

AXS-040 — Capacitive soil-moisture carrier PMOD module

Document purpose#

This document explains the axs-040-soil prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py), the project README, the TI ADS7042 documentation, and public documentation for the common "Capacitive Soil Moisture Sensor v1.2"-style probe.

The board is a design-stage prototype. Repository status is schematic generated, ERC clean, PCB layout not started, not released. There is no fabricated board and no assembled first article. Every voltage, code, and timing figure below is a design target or a vendor-typical figure to verify on real hardware, not proof that an assembled module works. The capacitive probe is a hobby-grade part with weak, inconsistent, and sometimes wrong documentation; its figures are marked vendor-typical throughout. The ADS7042, by contrast, is a fully specified TI part.

1. What the board does#

The board is a PMOD Type 2 (SPI, read-only) carrier that digitizes the slow analog output of a 3.3 V capacitive soil-moisture probe (v1.2-style breakout) with an on-carrier ADS7042 12-bit SAR ADC. The probe is a 555-timer astable oscillator driving a coplanar-trace capacitor; soil moisture changes the probe capacitance, which changes the rectified/filtered DC level on its AOUT pin. The carrier RC-filters AOUT (R1 1 kΩ + C3 10 nF) into the ADC's AINP, ties AINM to GND (single-ended), and uses AVDD = 3.3 V as the conversion reference, so full scale = 3.3 V. The ADS7042 has no configuration registers: drop ~CS, clock 16 SCLKs, and read 12 bits left-aligned after two leading zeros.

Higher moisture means higher probe capacitance means lower AOUT voltage: in-air reads highest, submerged-in-water reads lowest.

Functional block diagram#

PMOD host (3.3 V) J1                                    probe socket J2
  pin 6/12 3V3 ──┬── C1 100n ─ C2 1u (at U1) ──┬─────────> J2.1 VCC
                 │                             └ C4 100n, C5 10u (at J2)
  pin 1 ADC_CS_N ────────> ~CS  ┌──────────┐
  pin 4 SCK ─────────────> SCLK │ U1       │  SOIL_FILT   SOIL_AOUT
  pin 3 MISO <── R2 100R ── SDO │ ADS7042  │ AINP <── C3 ─┬── R1 1k ──< J2.3 AOUT
                                │ 12b SAR  │ AINM ── GND  │(10n to GND)
  pin 5/11 GND ────────────────>└──────────┘ <────────────┴──────────> J2.2 GND

2. Safety and scope boundaries#

• Verify the probe pinout with a DMM before ever plugging it into J2 (procedure in section 9.B). Three-pin probe breakouts genuinely differ between clones (VCC/GND/AOUT vs GND/VCC/AOUT and others), and the carrier order is fixed at 1 VCC, 2 GND, 3 AOUT. A VCC/GND swap reverse-biases the probe's 555/regulator and can destroy the probe; AOUT swapped onto VCC back-drives the probe's output filter and gives meaningless readings.
• Use a 3.3 V-capable probe. Many v1.2 clones ship with an NE555 (minimum supply 4.5 V) despite advertising 3.3–5.5 V; at 3.3 V these misbehave or stick. This is a documented, widespread known issue — see section 6.
• Do not submerge the probe above its marked line. The SMD area (555, regulator, filter) is not waterproof; typical listings mark a maximum immersion line on the PCB. Water on the electronics corrupts readings immediately and corrodes the probe permanently.
• Never feed 5 V into the PMOD connector or J2: J2 VCC is hard-wired to the PMOD 3V3 rail, and the ADS7042 absolute maximum AVDD/DVDD region is 3.6 V class — a 5 V probe supply experiment must be done entirely off-board.
• Keep the carrier and host dry; only the probe blade goes into soil or water, with a cable drip loop.
• A calibrated dry/wet mapping is probe-specific and drifts with temperature, soil type, insertion depth, and probe aging. Do not treat the output as an absolute volumetric-water-content instrument; it is a relative indicator unless calibrated against gravimetric samples.

3. Power and signal sequence#

1. The host (or bench supply) applies 3.3 V. C1/C2 decouple the ADS7042 AVDD/DVDD at the pins; C4/C5 hold the probe socket rail stiff against cable inductance and the probe's oscillator switching (probe draw is ~5 mA vendor-typical).
2. The probe's 555 astable runs (order of 1.5 MHz on v1.2-style boards); its on-probe diode/RC network converts the moisture-dependent capacitance into a DC level on AOUT. Power-on settling is of the order of 1 s, and moisture-step settling can be tens of seconds on defective clones missing the output bleed resistor.
3. R1 + C3 (1 kΩ + 10 nF, fc ≈ 16 kHz) low-pass the already-slow AOUT and double as the SAR charge bucket: C3 supplies the ADC's sample-capacitor inrush so R1's source impedance does not distort acquisition.
4. The host runs the fixed ADS7042 frame: ~CS falling edge samples AINP, 16 SCLKs shift out two leading zeros then 12 data bits, ~CS high ends the frame. Code = AINP / 3.3 V × 4095 (AVDD is the reference).
5. The host averages many samples (the probe is noisy and slow — a moving average is part of the intended lesson) and maps codes to moisture using the per-probe air/water calibration of section 9.E.

4. Interfaces and pin maps#

Note the J2 order differs from the flow carrier (AXS-039 uses VCC/SIGNAL/GND; this board uses VCC/GND/AOUT). Never assume a pigtail made for one carrier fits the other. #FLG01/#FLG02 are ERC power-flag symbols only, not physical parts.

Two usage contexts#

5. Component-by-component review#

External (not on the BOM, but part of the system under test):

6. Datasheet summary and design interpretation#

Honesty note: there is no authoritative datasheet for "Capacitive Soil Moisture Sensor v1.2". It is an open hardware design cloned by many factories with silent substitutions (NE555 for TLC555, missing bleed resistor, altered filter values). The TI documents above are authoritative for the chips; the probe-level numbers are community-measured typicals.

7. Expected values before bench testing#

8. Manual schematic and assembly review checklist#

• Confirm J1 pinout against PMOD Type 2: ~CS pin 1, MISO pin 3, SCK pin 4, pin 2 deliberately NC (no MOSI), GND 5/11, 3V3 6/12.
• Confirm U1 pin-1 orientation on the VSSOP-8 and that the assembly used ADS7042IDCUR (not a pin-different ADS7040/ADS7041 variant).
• Verify AINM (U1 pin 5) is at GND and AINP (pin 6) connects through R1 to J2.3 — a swap reads inverted/zero.
• Verify R1 = 1 kΩ, R2 = 100 Ω, C3 = 10 nF C0G in-circuit before power.
• When layout exists: C1/C2 at U1's pins, C4/C5 at J2, RC filter adjacent to AINP (this is an explicit README release item).
• Confirm J2 silkscreen marks 1 VCC / 2 GND / 3 AOUT unambiguously, and that it visibly differs from the AXS-039 carrier's VCC/SIGNAL/GND order.
• Inspect the probe: read the 555 marking under magnification. "TLC555" (or other CMOS 555) is acceptable for 3.3 V; "NE555" is a known-bad clone at 3.3 V — reject or replace the chip. Check the bleed resistor position is populated (clone-dependent; compare against the Cave Pearl writeup).
• Confirm the probe's maximum-immersion line is marked; if not, mark one yourself below the SMD area.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, probe identity (a photo of both probe faces is the practical "serial number" for clones), equipment IDs, ambient temperature, and operator for every run.

A. Unpowered inspection and resistance tests#

1. No probe, no host. Inspect solder under magnification; complete the section 8 checklist.
2. Measure 3V3-to-GND resistance at J1 in both meter polarities; investigate any hard short before power (bulk-cap charging gives a rising reading).
3. Measure J2.3 to U1 AINP: ≈1 kΩ (R1). Measure J1.3 (MISO) to U1 SDO: ≈100 Ω (R2).

B. Probe pin-order verification (before the probe ever touches J2)#

1. Find GND by continuity. Meter in continuity mode from each connector pin to the probe's exposed ground pour / mounting-hole ring / 555 pin 1 region. Exactly one connector pin should beep. Mark it.
2. Find VCC by current draw. Bench supply at 3.3 V with a 20 mA current limit, negative lead to the identified GND pin. Touch the positive lead to each remaining pin in turn: the VCC pin draws roughly 5 mA and the probe's oscillator starts; the AOUT pin draws almost nothing.
3. Confirm AOUT by DC level. With VCC and GND correctly powered, the remaining pin shows a stable DC level of roughly 1–3 V that rises when you pull the probe out of your hand's grip and falls when you grip the blade (your hand is "moisture").
4. Only now build/verify the pigtail so probe VCC→J2.1, GND→J2.2, AOUT→J2.3. Label the pigtail with the probe it was verified against.
5. Consequences of skipping this: VCC/GND reversal reverse-biases the probe's 555 and regulator (destructive); AOUT on the VCC pin means the probe is unpowered and the carrier rail back-drives its output network (misreads, possible stress); GND/AOUT swap grounds the output (reads 0) and floats the probe return through the signal path (garbage).

C. First power and SPI bring-up, standalone context#

1. Bench supply 3.3 V, 50 mA limit, to J1 pins 6/12 and 5/11. No probe. Current should be well under 1 mA.
2. Temporarily jumper J2.3 to GND. Drive SPI from a lab MCU or logic analyzer with pattern generator: ~CS low, 16 SCLK cycles (start at ≤1 MHz), ~CS high. Expect two leading zeros then 12 bits reading 0 ± a few LSB. Remove the jumper; the input now floats and codes will drift — that is expected, not a fault.
3. Optional midscale check: a bench divider (e.g. two 10 kΩ from 3V3 to GND) into J2.3 should read ≈2048 ± tolerance of the divider.
4. Capture one full frame on a logic analyzer and archive it: this is the golden reference for the HDL testbench.

D. Probe attach and dry/wet/water staircase#

1. Power off, plug in the verified probe, power on. Current rises to ≈5–6 mA. Log SOIL_FILT with a DMM and ADC codes simultaneously — the DMM validates the analog chain independently of SPI.
2. Wait ≥5 s after power-on before trusting readings (vendor-typical settling ≈1 s; margin costs nothing).
3. In air: expect the highest reading, vendor-typical ≈2.6–3.0 V (≈3200–3720 counts). Record the exact value — this is calibration endpoint A.
4. Submerged in water to the marked line, never above it: expect the lowest reading, vendor-typical ≈1.2–1.5 V (≈1490–1860 counts). Record — endpoint W. If the reading takes tens of seconds to move, suspect a missing bleed resistor on the clone (known issue).
5. Dry soil, then progressively moistened soil: readings must fall monotonically from near-A toward W as water is added. Absolute values are soil- and packing-dependent; only monotonicity and repeatability are pass criteria at this stage.
6. Repeat the air/water endpoints in the PMOD host context (ULX3S-class host, SPI master HDL, moving-average filter) and confirm host codes match the standalone MCU codes within noise.

E. Per-probe calibration and sensitivity characterization#

1. For each probe (calibration is per probe, not per design): record A (air) and W (water-at-line) as averaged codes at a noted temperature.
2. Map linearly: moisture % = 100 × (A − code) / (A − W), clamped to 0–100. This is a relative scale, not volumetric water content.
3. Characterize insertion depth: readings depend strongly on how much blade is buried (sensing field reaches only ~3–6 mm from the surface). Fix an insertion mark and always insert to it.
4. Characterize temperature: log a probe in stable moist soil across the room's day/night swing; expect visible drift. Note it in the record rather than pretending it away.
5. Repeatability: remove/reinsert the probe 5× at the mark in the same pot; the spread bounds the honest resolution of the measurement.
6. Release-only items (out of bench scope): waterproofing/conformal coating of the probe SMD area for field use, long-term corrosion, gravimetric soil calibration if absolute readings are ever claimed.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The carrier design is sound and appropriately conservative: a fully specified TI ADC with supply-as-reference, an RC filter that doubles as the SAR charge bucket, series protection on the one module-driven line, and generous decoupling at both the ADC and the probe socket. Every significant risk lives in the probe, not the carrier: unverified clone pin order (the single most likely way to destroy hardware on first plug-in), NE555 clones that silently fail at 3.3 V, missing bleed resistors that make response times absurd, and the complete absence of guaranteed specifications for the probe class. The bench plan therefore front-loads probe verification (section 9.B) before the probe ever touches the carrier, and treats the per-probe two-point air/water calibration — not any vendor number — as the authoritative transfer function. PCB layout, the HDL SPI master, and a purchased-probe pin-order confirmation remain open README items before any release claim.