← AXS-036

Circuit review & bench-test guide

AXS-036 — HX711 load cell ADC PMOD module

Document purpose#

This document explains the axs-036-hx711 prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the project README, and the Avia Semiconductor HX711 datasheet.

The board is a design-stage prototype: the schematic is generated and ERC is clean (0/0), but no PCB layout exists and no first article has been fabricated or assembled. Every value below is a design target to verify on real hardware, not proof that an assembled board works or meets the datasheet noise and drift numbers.

1. What the board does#

A 12-pin PMOD module carrying the Avia HX711 24-bit sigma-delta ADC for a Wheatstone-bridge load cell, in the datasheet's 3.3 V no-external-regulator configuration: VSUP = AVDD = DVDD = 3V3, VFB grounded, BASE open. The load cell's excitation is therefore the 3V3 rail itself, which keeps the measurement ratiometric (bridge output and ADC reference track the same rail).

The interface is neither SPI nor I2C: two wires, DOUT (module to host) and PD_SCK (host to module). DOUT falling signals data ready; the host then bit-bangs 25, 26 or 27 positive PD_SCK pulses to shift out 24 data bits MSB first, with the total pulse count selecting the next conversion's channel and gain. Only channel A is wired on this board; channel B inputs are grounded.

Functional block diagram#

4-wire load cell ──> J2 terminal (E+ E- A+ A-)
     E+ = 3V3 rail (excitation)      E- = GND
     A+/A- = SIG_P/SIG_M
                          v
                U1 HX711 (SOIC-16)             C1 100 nF on VBG
                PGA x128/x64 (ch A), x32 (ch B, unused)
                24-bit sigma-delta ADC, internal oscillator (XI=GND)
                RATE pin <── JP1 strap (GND = 10 Hz / 3V3 = 80 Hz)
                          │ DOUT ── R1 100 Ω ──> PMOD 1
                          │ PD_SCK <── PMOD 2, R2 10 kΩ pull-down
                          v
                J1 PMOD plug (3V3 / GND from host)
     Decoupling: C2 100 nF + C3 10 uF (AVDD), C4 100 nF (DVDD/VSUP)

2. Safety and scope boundaries#

• Voltages are low (3.3 V) and currents small; the dominant hazards are mechanical: a loaded load cell stores energy, and overloading a cell beyond its rated capacity can break it or the fixture. Respect the cell's safe overload rating and keep fingers out of the load path of lever fixtures.
• HX711 supplies are rated 2.6-5.5 V, but this module is strapped for a single 3.3 V rail; do not feed it 5 V from a host, because the PMOD 3V3 net is also the bridge excitation and the RATE strap reference.
• The channel A common-mode window is AGND+1.2 V to AVDD-1.3 V (1.2-2.0 V at 3.3 V). Only a bridge-type source centered near mid-rail is a valid input; do not wire arbitrary voltages into A+/A-.
• Weighing results from this plan are engineering sanity checks, not legal metrology. Nothing here substitutes for calibrated masses and a proper calibration procedure if real weights matter.
• Load-cell creep, zero drift, and temperature effects are properties of the cell as much as the ADC; do not attribute every drift to the board.

3. Power and signal sequence#

1. The host PMOD connector supplies 3V3 and GND. C2/C3 decouple AVDD, C4 decouples DVDD/VSUP, C1 bypasses the band-gap reference output VBG (1.25 V typ).
2. On-chip power-on reset runs at power-up. After any reset or power-down the part defaults to channel A, gain 128.
3. XI is grounded, selecting the internal oscillator; JP1 straps RATE: 1-2 to GND = 10 SPS (default bridge), 2-3 to 3V3 = 80 SPS.
4. R2 holds PD_SCK low while the host is unconfigured, so the part cannot float into power-down (PD_SCK high > 60 us = power down).
5. When a conversion completes, DOUT falls while PD_SCK is low. The host detects this (poll or edge interrupt) and clocks out the data.
6. Settling: allow 400 ms at 10 SPS / 50 ms at 80 SPS after power-up, reset, or any channel/gain change before trusting output data.

4. Interfaces and pin maps#

J1 PMOD plug (Type 1 GPIO footprint, custom map)#

J2 load-cell terminal (Phoenix MKDS 1,5/4-5,08)#

Red/black/green/white is the most common 4-wire convention but it is not universal (some vendors swap green/white or use blue/yellow); verify with the ohmmeter procedure in section 9.A before powering.

JP1 RATE strap (solder jumper, default bridged 1-2)#

Usage contexts covered by this plan#

In context (b), common the supply and MCU grounds at the module. In both contexts the same 3V3 rail excites the bridge, so supply noise enters the measurement only to the extent the ratiometric assumption breaks (see section 6 notes on AVDD noise).

5. Component-by-component review#

This is the complete reference-designator list from generate_design.py: U1, J1, J2, JP1, C1, C2, C3, C4, R1, R2 (plus ERC-only power flags #FLG01/#FLG02, schematic artifacts, not physical parts; JP1 is marked not-in-BOM/not-in-pos as a copper feature).

Layout-stage review items (open, no layout exists)#

• Keep INA+/INA- (SIG_P/SIG_M) routing short and symmetric, away from PD_SCK; analog pour under U1/J2 (already in the README release checklist).
• The datasheet reference PCB adds 100 R series resistors and 0.1 uF caps on the signal inputs (its R3/R4/C4); this schematic has no input RC filter on A+/A-. Acceptable for short leads; revisit if long unshielded cells show noise in section 9.F.
• Star the excitation (E+/E-) and decoupling returns so load-cell current does not share the signal ground path.

6. Datasheet summary and design interpretation#

Source consulted: HX711 datasheet (English), Avia Semiconductor (Xiamen) — the widely mirrored canonical PDF, fetched and read in full from SparkFun's CDN (the same URL recorded in generate_design.py). Avia has no practical public web presence; this vendor-distributed PDF is the de-facto reference.

Why PD_SCK jitter matters (T3 max = 50 us)#

Any single PD_SCK high period between 50 us and 60 us is out of spec, and one that stretches past 60 us silently power-cycles the chip mid-read: the read returns garbage and the channel/gain selection resets to A x128. A bit-banged MCU loop that takes an interrupt mid-pulse, or an RTOS context switch, can do exactly this. Mitigations: disable interrupts around the 25/27-pulse burst (a burst at 1 us/1 us takes ~50-54 us total), or use hardware (FPGA FSM in context (a), PIO/SPI-peripheral tricks on MCUs). Detect the failure mode by checking for DOUT stuck high afterward and by sanity-checking values.

7. First-transaction bring-up (exact bit-level sequence)#

Preconditions: power stable, PD_SCK low, >= 400 ms elapsed (10 SPS strap). Reset knowledge: after power-up the pending conversion is channel A, gain 128, so the very first read is already A x128 data.

1. Poll DOUT (PMOD 1). While a conversion is in progress DOUT is high; it falls when data is ready (at 10 SPS, within 100 ms plus settling).
2. Wait >= 0.1 us (T1), then issue pulse 1: PD_SCK high 1 us, low 1 us. DOUT presents the MSB (bit 23) within 0.1 us of the rising edge; sample it on the falling edge.
3. Repeat for 24 pulses total, sampling one bit per pulse, MSB first, assembling a 24-bit word.
4. Issue pulse 25 (do not sample data): this drives DOUT back high and commits "next conversion = channel A, gain 128". (26 pulses would select B x32; 27 selects A x64. Never fewer than 25 or more than 27.)
5. Sign-extend bit 23 into a signed 32-bit integer (two's complement).
6. DOUT stays high until the next conversion completes; repeat from step 1.

Plausible expected reading near zero load#

The reading is offset-dominated, not zero. Contributions at gain 128, 3.3 V excitation (1 count ≈ 1.54 nV input-referred):

So a healthy first reading is a stable signed value of roughly +/-1-2% of full scale (order 10^4-10^5 counts, sign either way), repeating within a few hundred counts p-p at 10 SPS. Red flags: exactly 0x000000 (DOUT stuck low/shorted), 0xFFFFFF or 0x7FFFFF/0x800000 saturation (open or swapped bridge wiring, missing excitation), or a value that jumps by millions of counts sample-to-sample (protocol/edge-sampling bug or T3 violation).

8. Manual schematic and assembly review checklist#

• Confirm U1 orientation and that pins strap exactly as: VFB (pin 4) to GND, BASE (pin 2) open, XI (pin 14) to GND, XO (pin 13) open, INB+/INB- (pins 10/9) to GND.
• Verify JP1 default bridge is 1-2 (RATE to GND = 10 SPS) and that pads 1 and 3 can never be bridged simultaneously without shorting the rail.
• Verify J2 order 1 = E+, 2 = E-, 3 = A+, 4 = A- and that silkscreen carries the names, not just numbers.
• Verify R2 pulls PD_SCK down (this is the opposite polarity of a typical SPI ~CS pull-up; a copy-paste error here puts the part to sleep).
• Verify R1 is in series between U1 DOUT (pin 12) and PMOD pin 1.
• Check C2/C3 land next to AVDD (pin 3), C4 next to DVDD/VSUP (pins 16/1), C1 next to VBG (pin 6) at layout time.
• Check PMOD pin 1 is an input on the host and pin 2 an output (Type 1 GPIO, custom map — document it in the host constraints file).
• Confirm #FLG01/#FLG02 and JP1 are excluded from BOM/placement outputs.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, load-cell model and rated output (mV/V), host identity, ambient temperature, and raw 24-bit readings (hex) for every step.

A. Load-cell identification and wiring check (unpowered)#

1. With the cell disconnected from the board, measure all six wire-pair resistances with an ohmmeter.
2. Expect a bridge: for a nominal 350 R cell, the output pair (A+ to A-) reads approximately the nominal 350 R, and the excitation pair (E+ to E-) usually reads noticeably higher (often ~400-450 R) because temperature-compensation resistors sit in series with the excitation arms. Each excitation-to-signal wire reads roughly half-bridge values. (1 kR-class cells scale accordingly.) The pair with the highest resistance is almost always excitation.
3. Map the identified pairs to colors and compare with red/black/green/white at J2; trust the ohmmeter over the colors. An open pair or a reading to the cell body (should be > 1 MR) fails the cell.
4. Board-side, unpowered: no 3V3-to-GND short; ~10 kR from PMOD 2 to GND (R2); ~100 R from U1 pin 12 pad to PMOD 1.

B. First power and first transaction#

Context (b) standalone first: bench supply 3.30 V, current limit 50 mA, MCU GPIOs on DOUT (input) and PD_SCK (output, driven low), common ground.

1. Power on with the load cell connected. Supply current should be roughly the bridge (3.3 V / R_bridge, ~8-10 mA for 350 R) plus ~1.5 mA for U1. Zero bridge current means no excitation; tens of mA extra means a fault.
2. Confirm DOUT toggles: high, then falling roughly every 100 ms (10 SPS).
3. Run the section 7 sequence; check the reading against the "plausible expected reading" table. Take 10 readings; they must agree within noise.
4. Press lightly on the cell: the value must move monotonically and return. If load moves the value negative when it should be positive, A+/A- are swapped (or the cell is mounted upside-down) — swap and re-verify.

Context (a) PMOD host: repeat steps 2-4 with the ECP5 host and the HDL FSM. Verify the constraints map PMOD 1 as input/2 as output before loading the bitstream.

C. Scope capture of the 2-wire protocol#

1. Scope CH1 on PD_SCK, CH2 on DOUT (module side of R1), trigger on DOUT falling.
2. Verify: DOUT falls while PD_SCK is low; first PD_SCK rise >= 0.1 us later; exactly 25 pulses (A x128); every high time within 0.2-50 us; DOUT bits change just after each rising edge and are stable at each falling edge; DOUT returns high on pulse 25.
3. Measure the worst-case PD_SCK high time over many bursts (infinite persistence). In context (b) with interrupts enabled, look for stretched pulses — this is the T3/60 us failure discussed in section 6.
4. Optionally capture a 27-pulse burst and confirm the next data frame scales by ~1/2 (gain 64 vs 128) for the same load, after 400 ms settling.

D. RATE strap and noise-vs-speed test#

1. At the default 10 SPS strap, log >= 5 minutes of zero-load readings. Expect on the order of tens of counts rms (datasheet 50 nV rms at gain 128 ≈ 32 counts at 3.3 V excitation); record the actual figure — clones and layout may be worse.
2. Re-strap JP1 to 2-3 (80 SPS), power-cycle, wait 50 ms settling, confirm DOUT now falls every ~12.5 ms, and repeat the log. Expect roughly double the noise (90 nV rms datasheet) plus worse mains rejection.
3. Return the strap to 1-2 for the release configuration and re-verify rate.

E. Tare drift, warm-up, and creep expectations#

Honest expectations — do not chase perfection out of a hobby-grade cell:

1. Warm-up: log from cold power-on for 30 minutes at zero load. The HX711 and the cell self-heat (the bridge dissipates ~30 mW); expect a drifting tare that flattens after 10-30 minutes. Tare after warm-up.
2. Temperature: datasheet offset drift is +/-6 nV/C input-referred (about 4 counts/C at gain 128, 3.3 V) plus gain drift +/-5 ppm/C — but the load cell's own zero drift (often +/-0.02-0.05% FS/C) dominates. Warm the assembly a few degrees and record counts/C for your setup.
3. Creep: apply a fixed mass for 30 minutes; hobby cells commonly creep 0.02-0.1% of the applied load over the first minutes. This is the cell, not the board; record it so software tare/re-zero policy can be set.

F. Span sanity check#

1. After warm-up and tare, apply a known mass (kitchen-scale calibration mass or a weighed object). Compute counts/gram; with cell sensitivity S (mV/V) and capacity M, predicted full-capacity counts = S x 3.3 mV x (2^23 / 12.9 mV) at gain 128 — verify within the cell's class (typically a few tenths of a percent) plus tare uncertainty.
2. Check linearity at ~25/50/100% of the test mass range and repeatability over five load/unload cycles.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic is a faithful implementation of the HX711 datasheet's no-external-regulator application: correct VFB/BASE/XI strapping, ratiometric 3V3 excitation, grounded unused channel B, sensible decoupling, and two protocol-hardening details that show good judgment — the PD_SCK pull-down (R2) that prevents an idle host from putting the part to sleep, and the series DOUT resistor (R1). Design-honesty items: C1 on VBG is not required in this mode (harmless), the datasheet reference layout's input RC filter on A+/A- is not fitted, and the datasheet itself contains a Fig. 2/Table 3 labeling inconsistency for the 27-pulse case that firmware authors should be warned about. Nothing is verified on hardware yet: noise, drift, the common-mode margin at 3.3 V excitation, and T3 timing robustness of both the FPGA FSM and MCU driver are the first-article questions section 9 exists to answer.