← AXS-035

Circuit review & bench-test guide

AXS-035 — MAX31855K thermocouple front end PMOD module

Document purpose#

This document explains the axs-035-max31855 prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the project README, and the MAX31855 datasheet.

The board is a design-stage prototype: the schematic is generated and ERC is clean (0/0), but no PCB layout exists and no first article has been fabricated or assembled. Every value below is a design target to verify on real hardware, not proof that an assembled board works or meets the datasheet accuracy numbers.

1. What the board does#

A 12-pin PMOD module that reads a type-K thermocouple through the Analog Devices (Maxim) MAX31855KASA+ cold-junction-compensated thermocouple-to-digital converter. The host sees the simplest possible SPI device: read-only, no MOSI. Dropping ~CS and clocking 32 bits returns a fixed frame containing the 14-bit compensated thermocouple temperature, a 12-bit cold-junction (die) temperature, and three fault bits (short-to-VCC, short-to-GND, open circuit).

It does not provide isolation, input over-voltage protection beyond the IC's own ratings, or any linearization beyond the MAX31855's straight-line approximation of the K-type curve.

Functional block diagram#

Type-K thermocouple ──> J2 screw terminal
                          │ TC_P / TC_M
                          ├── C2 10 nF differential filter
                          v
                    U1 MAX31855KASA+        C1 100 nF on 3V3
                    cold-junction comp,
                    14-bit ADC, faults
                          │ SO ── R1 100 Ω ──> PMOD 3 (MISO)
                          │ SCK <───────────── PMOD 4
                          │ ~CS <── R2 10 kΩ pull-up ── PMOD 1
                          v
                    J1 PMOD plug (3V3 / GND from host)

2. Safety and scope boundaries#

• The board is not isolated. The thermocouple tip is conductively connected to the measurement circuit; never attach the thermocouple to anything electrically live (mains heaters, powered busbars). Use an ungrounded (insulated-junction) probe when measuring metal that could carry potential.
• Heat sources used in testing (soldering iron, heat gun, boiling water) are burn hazards; the thermocouple wire itself conducts heat back to the terminal. Let probes cool before handling.
• MAX31855 absolute maximum on all pins is -0.3 V to VCC + 0.3 V and VCC absolute maximum is 4.0 V. Drive the module only from a 3.3 V rail (recommended range 3.0-3.6 V). It is not 5 V tolerant.
• ESD rating is +/-2 kV HBM only. Handle with normal ESD precautions; the T+/T- terminal is a user-facing input with no additional clamping on this board.
• A working bench reading is not a calibration. Nothing in this plan substitutes for a traceable temperature calibration if the module is used for anything beyond learning.

3. Power and signal sequence#

1. The host PMOD connector supplies 3V3 and GND (pins 6/12 and 5/11). C1 provides local decoupling at U1 VCC.
2. At power-on, U1's internal power-on reset runs (V_POR 2.0 V typ, 2.5 V max). Conversions begin automatically; no configuration exists or is needed. The datasheet requires waiting t_CONV_PU >= 200 ms after VCC is valid before trusting the first conversion.
3. Conversions run continuously in the background every t_CONV (70 ms typ, 100 ms max), converting the cold junction, the thermocouple, and running fault detection.
4. R2 pulls ~CS to 3V3 so SO stays released (high impedance) until the host drives ~CS low. While ~CS is low the output data is frozen; results update only while ~CS is high.
5. The host drops ~CS and issues 32 SCK cycles; U1 shifts the frame out on SO through R1 into PMOD pin 3 (MISO). D31 appears within t_DV (100 ns max) of the ~CS falling edge; each later bit is valid within t_DO (40 ns max) of the SCK falling edge, so the host samples on the SCK rising edge (SPI mode 0, CPOL=0/CPHA=0-compatible).

4. Interfaces and pin maps#

J1 PMOD plug (Type 2 SPI footprint, MOSI unused)#

J2 thermocouple terminal (Phoenix MKDS 1,5/2-5,08 footprint)#

Caution: ANSI type-K color coding uses red for the negative lead, which is the opposite of most electrical intuition, and IEC-color thermocouples use green/white instead. Do not trust color alone; the polarity test in section 9.C is the authoritative check.

Usage contexts covered by this plan#

Both contexts are electrically identical to the module; the difference is who provides 3V3 and who drives SCK/~CS. In context (b), common the bench supply GND with the MCU/adapter GND at the module.

5. Component-by-component review#

This is the complete reference-designator list from generate_design.py: U1, J1, J2, C1, C2, R1, R2 (plus ERC-only power flags #FLG01/#FLG02, which are schematic artifacts, not physical parts).

Cold-junction placement and thermal gradient review (layout-stage, open)#

The MAX31855 measures its own die temperature as the cold junction, so the accuracy budget assumes J2's screw contacts and U1's die are at the same temperature. The schematic already carries the layout note; since layout has not started, these are open review items:

• Keep J2 within a few mm of U1 with a continuous copper pour under both (datasheet: large ground plane improves accuracy; thermal island suggested in the README).
• No heat-generating parts near U1 (nothing on this board dissipates meaningfully — U1 itself is <= 1.5 mA x 3.6 V — but the host board and hot thermocouple wire conducting heat into J2 are real gradient sources).
• SOIC-8 theta_JA is 170 C/W on a JESD51-7 board; self-heating is ~0.5 mC at 3 mW and is negligible, so gradients, not self-heating, dominate the error.
• Route TC_P/TC_M as a short differential pair away from SCK.

6. Datasheet summary and design interpretation#

Source consulted: MAX31855 datasheet, Maxim Integrated document 19-5793 Rev 2, 2/12 — canonical copy at analog.com (product page: MAX31855 | Analog Devices); the identical Rev 2 PDF actually fetched and read for this review is the Adafruit-hosted mirror. Check for a newer revision before release.

7. SPI details and first-transaction bring-up#

Configuration: read-only, SPI mode 0 compatible (CPOL=0, CPHA=0), MSB first, SCK <= 5 MHz. Start bring-up at 500 kHz-1 MHz. There is no MOSI and no command byte; the transaction is:

1. ~CS high, SCK idle low, wait >= 200 ms after power-on.
2. Drive ~CS low. D31 appears on SO within 100 ns.
3. Issue exactly 32 SCK cycles, sampling SO on each rising edge (a 14-cycle read returns only the thermocouple field; do 32 to get faults + cold junction).
4. Raise ~CS. Keep it high >= 200 ns (in practice, milliseconds, so the next conversion can update the register).

32-bit frame layout (datasheet Tables 2/3)#

Expected first response at room temperature#

With the thermocouple tip and the board both at ~25.0 C: thermocouple field = 25.00/0.25 = 100 = 0b00000001100100; internal field = 25.0000/0.0625 = 400 = 0x190. Ideal frame: 0x01901900 (fault bits all 0). Realistically both fields read "roughly room temperature, within a couple of C, all fault bits 0, D17 = D3 = 0" — e.g. anything decoding to 20-28 C on both fields on a normal bench. Immediate red flags: 0xFFFFFFFF or 0x00000000 (wiring/MISO problem, not a plausible reading), D17/D3 set (bit-alignment error in the host), or the two temperature fields wildly disagreeing at ambient.

8. Manual schematic and assembly review checklist#

• Confirm U1 is exactly MAX31855KASA+ (K suffix): another letter is a different thermocouple type with different gain.
• Confirm U1 pin-1 orientation; verify pin 8 (DNC) is left unconnected.
• Verify J2 pin 1 = TC_P = T+ and the silkscreen marks polarity.
• Verify C2 sits directly across TC_P/TC_M near U1 pins 2/3, and is C0G.
• Verify C1 lands close to U1 pin 4 (VCC) with a short GND return.
• Verify R1 is in series between U1 SO (pin 7) and PMOD pin 3, and R2 pulls CS_N to 3V3 (not GND).
• Check PMOD pin 1 = ~CS, 3 = MISO, 4 = SCK against the host's PMOD pinout (Type 2 SPI); pin 2 must be unconnected on the module.
• Layout stage: J2/U1 isothermal placement, ground pour, differential TC routing, SCK kept away from TC inputs (section 5 notes).
• Confirm #FLG01/#FLG02 are excluded from BOM and placement outputs.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host/adapter identity, ambient temperature, and raw 32-bit frames (hex) for every step.

A. Unpowered inspection and resistance tests#

1. Visual inspection under magnification: U1 orientation, solder bridges on the SOIC-8, C2 across the TC nets.
2. Measure 3V3-to-GND resistance (expect high, no hard short in either meter polarity).
3. With no thermocouple fitted, J2-1 to J2-2 should read as C2 charging (high/open at DC). J2-1 or J2-2 to GND must not be a short.
4. Verify ~10 kΩ from CS_N (PMOD pin 1) to 3V3 and ~100 Ω from U1 pin 7 pad to PMOD pin 3.

B. First power and first transaction#

Context (b) standalone first: bench supply 3.30 V, current limit 20 mA, into PMOD 3V3/GND; lab MCU or SPI adapter on ~CS/SCK/MISO, common ground.

1. Power on with no thermocouple fitted. Supply current should be roughly 0.9-1.5 mA (I_CC) — tens of mA indicates a fault; stop.
2. Wait >= 200 ms. Run the section 7 transaction at <= 1 MHz.
3. Expect D16 = 1 and D0 (OC) = 1 because no thermocouple is fitted, with a sane internal temperature in D[15:4]. Datasheet: with T+/T- unconnected the thermocouple sign bit D31 reads 0 and D[30:18] read all 1s.
4. Fit the thermocouple in J2 (T+ to pin 1). Re-read: fault bits clear, both temperature fields near ambient (section 7 expected response).
5. Scope check: confirm SO transitions follow SCK falling edges and the sampled mode is 0; try 5 MHz only after 1 MHz is solid.

Context (a) PMOD host: repeat steps 2-4 with the module plugged into the ECP5 host PMOD (3.3 V bank), using the HDL SPI master. Verify the host PMOD really supplies 3.3 V before insertion.

C. Thermocouple polarity test#

1. With the reading stable at ambient, pinch the thermocouple tip between two fingers (or briefly bring a heat gun near it). The reading must move up by several degrees within a couple of conversions.
2. If the reading moves down when the junction warms, the leads are swapped at J2: the thermoelectric voltage is inverted. Swap them and repeat. Do not rely on wire colors (ANSI type K: red is negative).
3. Let the tip cool; the reading must return to ambient.

D. Ice-point and boiling-point sanity checks#

1. 0 C: stirred ice-water slush (crushed ice, just enough water), tip in the slush not touching the container. Expect 0.0 C +/- 2 C per the datasheet K-type accuracy, plus the probe's own tolerance (a class 2 K probe adds up to +/-2.5 C — record the probe class).
2. ~100 C: freshly boiling water, tip submerged, not touching the pot. Expect ~100 C +/- 2 C at sea level; the boiling point drops roughly 1 C per 285 m of altitude (e.g. ~96.7 C at 1000 m), so correct for local altitude/pressure before judging.
3. Record the internal (cold-junction) field during both tests; it should stay near room temperature. If it tracks the bath, heat is conducting up the wires into J2/U1 — a cold-junction gradient problem.

E. Open-circuit and fault-bit tests#

1. While polling, unscrew one thermocouple lead from J2. Within one or two conversions (t_CONV <= 100 ms each) D0 (OC) must go to 1 and D16 (fault) must go to 1. Reconnect; both must clear.
2. Optional, current-limited and deliberate: short T+ to GND at J2 (expect D1 SCG + D16), then T+ to 3V3 through the probe (expect D2 SCV + D16). Restore wiring and confirm all faults clear and readings return.
3. Confirm the host software surfaces D16 and refuses to report the temperature fields as valid while any fault bit is set.

F. Noise, gradient, and rate characterization (pre-release)#

1. Log 10 minutes of readings at ambient; expect the thermocouple field to sit within 1-2 LSB (0.25-0.5 C) peak-to-peak on a quiet bench.
2. Repeat with the host FPGA busy (context (a)) to check SCK/host-noise coupling; a visible worsening points at layout/filtering, C1/C2.
3. Blow warm air across the board (not the tip) and watch for reading shifts with a constant-temperature tip: quantifies the cold-junction gradient error for the eventual layout.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic follows the MAX31855 datasheet's application guidance closely: 0.1 uF supply bypass (C1), the rev-2-recommended 10 nF differential input filter (C2), a released bus by default (R2), and a protected sensor-driven data line (R1). The design's honest weak points are all layout-stage and verification-stage: the cold-junction isothermal placement of J2 and U1 is a note, not yet copper; no first article exists, so the +/-2 C accuracy class, 5 MHz operation through R1, fault-bit timing, and gradient behavior are all unverified targets. The polarity, ice/boiling, and open-circuit tests in section 9 are the minimum evidence needed before trusting this module to teach correct numbers.