← AXS-033

Circuit review & bench-test guide

AXS-033 — Build-your-own sigma-delta ADC lab PMOD module

Document purpose#

This document explains the axs-033-sigma-delta prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the implemented schematic generator (generate_design.py), the module README, the sensor-line conventions in ../README.md, and the verified Pmod-spec notes in ../../pmod-common/PMOD-SPEC-NOTES.md.

This board is a schematic-complete prototype only. It has not been laid out, fabricated, assembled, or bench-verified. Repository status: schematic generated, ERC clean (0 errors / 0 warnings), netlist reviewed; PCB layout not started. Every numeric value below is a design target, not a measurement. Comparator figures were verified against the fetched TI TLV3501 datasheet (SBOS321E); see Section 6.

1. What the board does#

This module is half of an ADC; the FPGA is the other half. A TI TLV3501 4.5 ns rail-to-rail comparator and an RC integrator (R2 = 10 kOhm, C1 = 10 nF, tau = 100 us) form the analog part of a first-order sigma-delta modulator whose loop closes through the FPGA fabric: the comparator's 1-bit answer (SD_CMP, PMOD pin 1) is registered by a fabric flip-flop each clock, and the registered bit (SD_FB, PMOD pin 2) drives back through R2 into the integrator node on the comparator's inverting input. With the loop running, the RC node servos to the input voltage and the density of 1s in the bit stream equals Vin/3.3. A CIC or plain-averaging decimator in fabric turns the stream into samples; oversampling ratio trades rate for ENOB. DNP pads (R3, C2) allow time-constant experiments.

The analog input arrives on J2 (AIN/GND/3V3, 0 to 3.3 V range) through R1 into the comparator's non-inverting input.

Functional block diagram#

J2 ANALOG IN                              PMOD host (AruviX ECP5 rev-A or
 1 AIN --- R1 10k --- CMP_INP --->|+ \        any 3.3 V Digilent socket)
 2 GND                            |   \ U1        |
 3 3V3                            |TLV3501>-- R4 100R --> J1 pin 1 SD_CMP
             SD_INT ------------->|- /  (CMP_OUT)         |
               |                  |                   [fabric FF, clk Fclk]
               +-- C1 10n --- GND |SHDN=GND               |
               |   (C2 22n DNP)   |V+=3V3 (C3 100n)       v
               +-- R2 10k ------------------------<-- J1 pin 2 SD_FB
                   (R3 4.7k DNP)                     (host-driven feedback)

Loop: SD_FB <= SD_CMP registered at Fclk; 1-density of SD_CMP = Vin/3.3

2. Safety and scope boundaries#

• This is an unfabricated design; no bench evidence exists yet. All loop behavior below is predicted from the schematic and datasheet.
• 3.3 V domain only. The TLV3501 absolute maximum supply is 5.5 V and its inputs are diode-clamped to the rails (signals beyond the rails must be limited to 10 mA); keep J2 AIN within 0 to 3.3 V. R1 gives roughly 10 kOhm of accidental-overdrive limiting, which covers modest mistakes, not connecting a lab supply set to 12 V.
• J2 pin 3 exposes the module's 3.3 V rail for sensor excitation. It is the host's PMOD rail: never back-drive it from an external supply and keep total draw within the ~100 mA PMOD guidance.
• SD_FB is a host-driven pin into a module that also drives SD_CMP. Do not configure both PMOD pins as outputs on the host; pin 1 is module-driven (via R4), pin 2 is host-driven, and swapping them in the constraint file creates driver-versus-driver contention through only R4.
• The TLV3501 toggles in nanoseconds; probe with short grounds and expect to see (and dismiss) probe-artifact ringing before blaming the board.
• An earth-referenced scope ground goes only to module GND.

3. Signal and power sequence, and how the loop works#

1. The host applies 3.3 V/GND at J1. C3 decouples the comparator supply.
2. SHDN is hard-wired to GND. Per the datasheet the part is disabled when SHDN is within 0.9 V of V+ and enabled when more than 1.7 V below V+; at GND on a 3.3 V rail it is firmly enabled. (The schematic comment says the same; the polarity is verified, not assumed.)
3. Before the host drives SD_FB, the integrator node floats toward whatever the comparator input leakage (pA) and board leakage dictate; SD_CMP then sits at a rail. This is normal pre-loop behavior.
4. The host loads the loop fabric: a single flip-flop clocked at Fclk samples SD_CMP and drives the registered value onto SD_FB. That is the entire modulator: the flip-flop is the quantizer memory (and synchronizer), R2/C1 is the loop integrator, U1 is the quantizer.
5. Closed-loop action, one clock at a time: if Vin (through R1, at +in) is above the integrator node (at -in), the comparator outputs 1; the fabric registers it and drives SD_FB = 1 = 3.3 V through R2, charging C1 upward. When the node crosses above Vin the comparator flips to 0, the fabric feeds back 0 V, and C1 discharges. The node therefore saws in a small ripple band around Vin, and charge balance forces the average fed-back voltage - 3.3 V times the 1-density - to equal Vin. Hence 1-density = Vin/3.3.
6. A decimator (CIC, or a plain counter over N clocks) converts density to a code: code = (ones in N)/N x full scale. OSR = N sets the resolution/rate trade.

Loop design numbers#

• tau = R2 x C1 = 10 kOhm x 10 nF = 100 us; the schematic note requires Fclk >> 1/tau = 10 kHz. At Fclk = 1 MHz each clock moves the node by at most about Vdd x Tclk/tau = 3.3 x (1 us/100 us) = 33 mV of ripple; at 10 MHz, about 3.3 mV. Higher Fclk means smaller ripple and better ENOB at the same output rate.
• The DNP pads change tau: R3 (4.7 kOhm) in parallel with R2 gives about 3.2 kOhm (tau = 32 us, more ripple, faster tracking); C2 (22 nF) in parallel with C1 gives 32 nF (tau = 320 us, less ripple, slower).
• The feedback levels are the FPGA pad's VOL/VOH, not ideal 0/3.3 V, and the comparator sees Vin through R1 with pA-class bias current (no meaningful drop). Driver drop appears directly as gain error in the transfer function - one of the things the DC sweep measures.

4. Interfaces and pin map#

Bench contexts: either a PMOD host (AruviX ECP5 rev-A or any 3.3 V Digilent-compatible PMOD socket) running the loop flip-flop, or a bench 3.3 V current-limited supply plus DMM/oscilloscope/logic analyzer for open-loop checks (the full ADC only exists with a host closing the loop).

No test points exist yet. The essential probe nodes are SD_INT (the R2/C1 junction at U1 -in), CMP_INP (after R1), CMP_OUT (before R4), and the two J1 signal pins; layout should promote SD_INT and CMP_OUT to test points.

5. Component-by-component review#

TLV3501 key datasheet parameters (verified from TI SBOS321E)#

6. Datasheet summary and design interpretation#

Note the repository convention check: the module is labeled PMOD Type 1 (GPIO, custom two-pin map), which PMOD-SPEC-NOTES.md sanctions since spec types are conventions; the pin-1-module-driven / pin-2-host-driven asymmetry is the item to keep prominent in the HDL constraints.

7. Expected values before bench testing#

Example loop plan: Fclk = 1 MHz flip-flop clock, tau = 100 us (R2/C1), decimation N = 1024 (output about 977 Sa/s).

8. Manual schematic and assembly review checklist#

• Verify J1 pin-1 orientation against PMOD-SPEC-NOTES.md before power.
• Verify U1 orientation on the SOT-23-6 (pin 1 = -IN to SD_INT, pin 3 = +IN to CMP_INP, pin 4 = V+, pin 2 = V-, pin 5 = OUT, pin 6 = SHDN to GND). An input swap is invisible to an ohmmeter and fatal to the loop.
• Audit DNP status: R3 and C2 pads must be empty in the baseline build; record it, because tau silently changes if they are populated.
• Measure R1, R2, R4 values; buzz SD_FB (J1 pin 2) through R2 to SD_INT, SD_INT to C1 to GND, CMP_OUT through R4 to J1 pin 1, AIN (J2 pin 1) through R1 to +in.
• Confirm C3 sits against U1's V+ (layout review) and the R2/C1 node is tight against U1 -in (the README's explicit layout note).
• Confirm J1 pins 3, 4, 7-10 are NC and J2 pin 3 really is the rail.
• Measure 3V3-GND resistance for shorts before power.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record captures with board serial, equipment IDs, Fclk, decimation N, DNP audit, and operator.

A. Unpowered inspection and resistance tests#

1. Complete the Section 8 checklist under magnification.
2. Measure 3V3-to-GND in both polarities; investigate hard shorts.
3. Verify: J1 pin 2 to SD_INT about 10 kOhm (R2); J1 pin 1 to U1 pin 5 about 100 Ohm (R4); J2 pin 1 to U1 pin 3 about 10 kOhm (R1).

B. Static power-up and open-loop comparator checks (bench supply)#

1. Feed 3.3 V, current-limited to about 20 mA, into J1 pins 6/12 vs 5/11. Expect about 3.2 mA (5 mA max) - the TLV3501 idles hot by sensor-module standards; that is normal.
2. Drive AIN from a calibrated source at 1.000 V. Manually hold SD_FB (J1 pin 2) at GND through a jumper: SD_INT discharges to 0 V and SD_CMP must read high (about 3.3 V). Hold SD_FB at 3.3 V: SD_INT charges toward 3.3 V with a visible tau = 100 us exponential and SD_CMP must fall once the node passes about 1 V.
3. This validates polarity (+in vs -in), the integrator path, and the output stage before any HDL is trusted.

C. Closed-loop test with the FPGA feedback bit#

1. Attach the PMOD host. Load the minimal loop fabric: one flip-flop clocked at Fclk = 1 MHz sampling SD_CMP, its Q driving SD_FB; a ones-counter over N = 1024 clocks publishing the density code. (Two flip-flops in series on SD_CMP before the feedback tap is the more robust variant - it costs one clock of loop delay and removes metastability from the fed-back bit; note which variant ran.)
2. With AIN at 1.650 V (mid-scale), scope SD_CMP and SD_FB together: SD_FB must be SD_CMP delayed by one clock (or two, per the variant), and the pattern near mid-scale approaches an alternating 1010 idle tone at Fclk/2.
3. Scope SD_INT: a small sawtooth centered on 1.65 V, about 33 mV p-p at 1 MHz, each segment an exponential piece of the tau = 100 us curve. The node visibly "servos" - move AIN slowly and the sawtooth's center tracks it. This is the loop working.
4. Read the density code: expect 0.500 x N counts within offset/gain error. Sweep Fclk (250 kHz, 1 MHz, 4 MHz, 10 MHz) and confirm ripple shrinks proportionally while density stays put; check R4/cable edges still give clean levels at the top rate.
5. Stop-clock behavior: freeze Fclk with SD_FB stuck at 1 - SD_INT rails to 3.3 V and SD_CMP parks low; resume and the loop reacquires within a few tau. No state is retained anywhere but C1 - a feature to show, not a bug.

D. DC sweep linearity procedure#

1. Drive AIN from a calibrated, low-noise source (a good DAC or a 10-turn pot from J2's own 3V3 with a DMM monitoring the actual voltage; log the DMM value, not the setpoint).
2. Fix Fclk (recommend 4 MHz or more so ripple, about 8 mV, is small against the target resolution) and a decimation long enough to average idle tones (N of 65536 or average many N = 1024 frames).
3. Step AIN from 0 to 3.300 V in 33 mV steps (101 points, 1% of FS), plus fine 3 mV steps over the bottom 30 mV and top 30 mV where offset and hysteresis effects concentrate.
4. At each point record the DMM voltage and the averaged density (or filtered output code). Plot code vs voltage.
5. Fit a line to the central 10-90% of the sweep. Report offset error (intercept, in mV of input), gain error (slope vs the ideal density = Vin/3.3), and INL (max residual from the fit, in mV and in equivalent LSB at the chosen resolution). Targets: offset within the comparator's +/-6.5 mV max Vos budget (typically a few mV), gain error consistent with the host pad's VOL/VOH, INL smooth and sub-0.1%-class mid-range - all first-article discoveries, not guarantees.
6. Repeat one sweep at a second Fclk and, if experimenting, with R3 or C2 populated (record the DNP change); linearity should be Fclk-insensitive once ripple is small.

E. TLV3501 offset and hysteresis characterization notes#

1. The comparator's input offset (up to +/-6.5 mV max per the datasheet, +/-1 mV typical) adds directly to the loop's null: the integrator servos to Vin + Vos, so the whole transfer curve shifts horizontally by Vos. It appears as the intercept in the Section D fit and cannot be distinguished from source error without a better reference - hence the calibrated-source requirement.
2. The TLV3501's built-in hysteresis (6 mV typical per the datasheet) does not simply add to offset: within the loop it makes the comparator hold its previous decision until the integrator moves about 6 mV past the crossing, which lengthens limit cycles (consecutive identical bits), raises ripple slightly above the pure RC prediction, and strengthens idle tones. On average it cancels mid-range, but near the ends of the sweep the asymmetry stops canceling: within roughly (Vos + hysteresis/2) of 0 V and 3.3 V, about 4-10 mV, expect the code to reach hard 0/1 density early or flatten - a visible foot/shoulder on the plot.
3. Measure it: at a few fine points near each end, record the density deviation from the fit line and the run-length statistics of SD_CMP (longer runs = hysteresis at work). Compare the observed foot width against the 4-10 mV expectation; a much larger foot suggests supply noise coupling into the threshold (check C3) rather than the part.
4. Temperature note: Vos drifts about +/-5 uV/C per the datasheet - negligible at bench temperatures; do not chase mV-level drift there.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic is a textbook first-order sigma-delta front end split honestly across the connector: the only analog state is C1, the only quantizer is U1, and the flip-flop that makes it an ADC deliberately lives in the student's fabric. Component choices back the lesson - C0G integrator parts, a verified-polarity SHDN strap, series protection on the one module-driven pin, and DNP pads that turn tau into an experiment rather than a constant. The comparator datasheet numbers bound what the lab can teach: +/-6.5 mV max offset and 6 mV typical hysteresis put a floor of a few mV on absolute accuracy at the range ends, while 4.5 ns and 80 MHz mean the loop clock, not the comparator, always limits speed. The principal open risks are the unstarted layout (the R2/C1 node must be tight against -in, and fast edges need a solid return path), the unverified linearity targets, host-pad VOL/VOH gain error, and the pin-1/pin-2 direction asymmetry as a standing constraints-file hazard. Until a fabricated board passes Sections 9.A-9.D, every number here remains a target.