← AXS-030

Circuit review & bench-test guide

AXS-030 — Piezo contact mic PMOD module

Document purpose#

This document explains the axs-030-piezo prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the implemented schematic generator (generate_design.py), the module README, the sensor-line conventions in ../README.md, and the verified Pmod-spec notes in ../../pmod-common/PMOD-SPEC-NOTES.md.

This board is a schematic-complete prototype only. It has not been laid out, fabricated, assembled, or bench-verified. Repository status: schematic generated, ERC clean (0 errors / 0 warnings), netlist reviewed; PCB layout not started. Every numeric value below is a design target, not a measurement. Active-part figures were verified against the fetched TI ADS7042 datasheet (SBAS608C) and Nexperia BAT54S datasheet (1 July 2022); see Section 6.

1. What the board does#

An external piezo disc (contact microphone, attached at J2) is referenced to a resistive mid-rail so both polarities of its swing digitize, clamped to the rails by a BAT54S Schottky pair against the tens of volts a struck disc can generate open-circuit, and sampled single-ended by a TI ADS7042 12-bit, up-to-1-MSPS SAR ADC. The module is a PMOD Type 2 (SPI) plug, read-only: the ADS7042 has no registers and no data input, so MOSI is not connected. Every ~CS-framed burst returns one sample; the fabric lesson is a free-running sampler FSM, FIFO, and envelope/knock detection.

Functional block diagram#

PMOD host (AruviX ECP5 rev-A or any 3.3 V Digilent-compatible socket)
   |
   J1 (PMOD Type 2 plug, read-only SPI)
   |  pin 1 ~CS  (host out, R5 10k pull-up to 3V3)
   |  pin 3 MISO (module out) <-- R4 100R <-- ADC_SDO
   |  pin 4 SCK  (host out)
   |
   |         3V3                       3V3
   |          |                         |
   |         R2 1M                   AVDD/DVDD (C1 100n, C2 1u)
   |          |                         |
   | VMID ----+----- R1 1M ----- PIEZO -+--> U1 ADS7042 AINP
   |          |                   |         U1 AINM --> GND
   |         R3 1M            D1 BAT54S
   |          |               common pin 3 = PIEZO
   |         GND              A1(pin1)->GND, K2(pin2)->3V3
   |
   J2 pin 1 PIEZO (disc signal), pin 2 GND (disc brass)

2. Safety and scope boundaries#

• This is an unfabricated design. The clamp, bias, and streaming numbers below are targets; the first assembled article must earn them on the bench.
• A piezo disc is a genuine high-voltage source when struck: tens of volts open-circuit is normal for a hard knock. Never connect a disc directly to an unprotected input, and treat "abuse" strike tests on the assembled module as deliberately bounded experiments (Section 9.E), not routine handling. Do not hammer the disc with the clamp unverified.
• The clamp routes strike energy into the 3.3 V rail through D1. Large repeated strikes pump charge into the rail; on a bench supply this is absorbed, but on a PMOD host it lands on the host's 3.3 V regulator. Characterize strike behavior on a current-limited bench supply first.
• 3.3 V logic only. ADS7042 absolute maximum on AVDD/DVDD is 3.9 V and AINP must stay within -0.3 V to AVDD + 0.3 V; the clamp exists to keep the input inside that window.
• ESD-sensitive parts (ADS7042 HBM +/-2 kV). Grounded mat and strap.
• Keep module draw within the ~100 mA PMOD guidance; this design's budget is ~1-2 mA.
• Nothing here is a calibrated acoustic or vibration measurement.

3. Signal and power sequence#

1. The host applies 3.3 V (J1 pins 6/12) and GND (pins 5/11). C1 (100 nF) and C2 (1 uF) decouple AVDD/DVDD; the datasheet requires at least 200 nF at AVDD because AVDD is also the ADC reference.
2. R2/R3 (1 MOhm each) establish VMID at 3.3/2 = 1.65 V, burning only 1.65 uA. R1 (1 MOhm) references the piezo node (PIEZO) to VMID, so the disc's AC swing rides on a mid-scale DC level and both polarities land inside the ADC's 0-AVDD range.
3. D1 (BAT54S series pair, common pin to PIEZO) clamps the node roughly one Schottky drop below GND and above 3V3 during strikes.
4. R5 (10 kOhm) pulls ~CS to 3V3 so the ADC stays deselected, its SDO released, until the host actively drives ~CS - important while the FPGA is unconfigured and its pins float.
5. On the first ~CS falling edge after power-up the ADS7042 runs its offset calibration; the datasheet requires at least 16 SCLKs in that first frame (SDO stays low during it) or the calibration register is not updated.
6. Each subsequent ~CS-framed burst returns one sample: two leading zeros, then D11..D0 MSB-first on SCLK falling edges, SDO low after the 14th SCLK, 3-state on ~CS rising. The 16-clock frame named in the schematic notes satisfies the 14-clock minimum with two idle clocks.
7. SDO reaches the host through R4 (100 Ohm), the sensor-line series rule on every module-driven pin.

Why the bias and clamp are both needed#

Without R1-R3 the disc's charge has no DC reference: the node drifts to whatever leakage dictates, half of every waveform clips at the rails or is lost below 0, and the quiescent code is meaningless. Without D1 a single hard strike drives the node tens of volts past the rails; the ADC's internal ESD diodes would take the full surge, current-limited only by the disc's own source impedance, an abuse the datasheet does not license. The 1 MOhm bias also matters acoustically: with a typical disc capacitance in the tens of nF, the roughly 1.5 MOhm Thevenin load (R1 in series with R2||R3) sets a low-frequency corner of a few hertz (disc-dependent - unverified estimate; measure with the actual disc), so knock transients pass undistorted.

4. Interfaces and pin map#

Bench contexts: either a PMOD host (AruviX ECP5 rev-A or any 3.3 V Digilent-compatible PMOD socket) running a sampler FSM, or a bench 3.3 V current-limited supply plus DMM/oscilloscope/logic analyzer, with any SPI master (or manual ~CS/SCK from a generator) driving the read-only frame.

There are no test points in the schematic. Probe at J2 pin 1 (the PIEZO node), the R2/R3 junction (VMID), and the J1 pins until layout adds them.

5. Component-by-component review#

ADS7042 key datasheet parameters (verified from TI SBAS608C)#

BAT54S key datasheet parameters (verified from Nexperia, 1 July 2022)#

6. Datasheet summary and design interpretation#

7. Expected values before bench testing#

Example clock plan: SCLK = 8 MHz, 16-clock frames, ~500 kSPS free-running.

8. Manual schematic and assembly review checklist#

• Verify J1 pin-1 orientation against PMOD-SPEC-NOTES.md before power.
• Verify D1 orientation explicitly: SOT-23 pin 1 (A1) to GND, pin 2 (K2) to 3V3, pin 3 (common) to the PIEZO net. A rotated part is the classic failure and it biases the input wrong quietly.
• Measure R1, R2, R3 in-circuit before connecting anything (the three 1 MOhm values dominate the bias arithmetic).
• Buzz: J2 pin 1 to D1 pin 3 to U1 AINP; U1 AINM to GND; SDO through R4 to J1 pin 3; ~CS from J1 pin 1 to U1 with R5 to 3V3; SCK from J1 pin 4.
• Confirm U1 orientation and that AVDD/DVDD both reach 3V3, with C1/C2 adjacent to the supply pins (layout review: keep C1 nearest AVDD, since AVDD is the reference).
• Confirm J1 pins 2 and 7-10 are NC.
• Check no solder bridges around the VSSOP-8 (0.5 mm pitch).

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record captures with board serial, equipment IDs, disc identity, and operator.

A. Unpowered inspection and resistance tests#

1. Complete the Section 8 checklist under magnification.
2. Measure 3V3-to-GND in both polarities; investigate hard shorts.
3. Measure J2 pin 1 to GND and to 3V3 in both meter polarities: expect megohm-class readings one way and a Schottky junction (about 0.2-0.4 V on diode test) the other way through each half of D1. This is the clamp-orientation check with no power applied: diode-test from GND (red on GND probe polarity conducting toward the node) and from the node to 3V3 must both show one forward drop; the reverse directions must read open.
4. Measure J1 pin 1 to 3V3: about 10 kOhm (R5). J1 pin 3 to U1 SDO: about 100 Ohm (R4).

B. Bias midpoint verification (bench supply, no disc, no host)#

1. Feed 3.3 V, current-limited to about 20 mA, into J1 pins 6/12 vs 5/11.
2. Compute the expectation from the measured resistors: VMID = 3.3 x R3/(R2+R3) with the values recorded in step A; nominal 1.65 V.
3. Measure VMID at the R2/R3 junction and the PIEZO node DC at J2 pin 1. Both must agree with the computed midpoint after correcting for meter loading (a 10 MOhm DMM reads the PIEZO node about 2.4% low through the 1.5 MOhm source impedance). A high-impedance buffer or 10 GOhm meter removes the correction.
4. A PIEZO node stuck near 0 V or 3.3 V with a correct VMID indicts D1 orientation or a bridge, not the divider.

C. ADC bring-up and frame capture#

1. Attach the PMOD host (or SPI master). Hold ~CS high, confirm MISO is released (R4/R5 make it read high-impedance, not driven).
2. Issue the power-up calibration frame first: ~CS low with at least 16 SCLKs (the design FSM should always begin with one 32-clock or 16-clock dummy frame). SDO stays low throughout - do not log it as a sample.
3. Run continuous 16-clock frames at moderate SCLK (1-8 MHz). Logic analyzer: verify 2 leading zeros, 12 data bits MSB-first launched on SCLK falling edges, SDO low after clock 14, 3-state after ~CS rises, and at least 200 ns of ~CS-high between frames.
4. Confirm the quiescent code sits near 2048 with only a few LSB of noise and matches the Section B midpoint via code x 806 uV.
5. Optionally raise SCLK toward 16 MHz / 1 MSPS and confirm the data stays clean (R4 slew, layout permitting).

D. Knock waveform capture via streaming#

1. Connect the piezo disc to J2 and tape or clamp it to a surface (a contact mic must be mechanically coupled to something).
2. Stream continuously into the FIFO at a rate comfortably above the disc's resonance - 100 kSPS or more is ample for single-digit-kHz bursts.
3. Confirm the resting stream stays near mid-scale (2048-class codes).
4. Knock the surface lightly. Expect a decaying oscillatory burst centered on the quiescent code: an initial swing whose polarity depends on disc wiring, ringing at the disc/surface resonance, decaying over tens of milliseconds back to mid-scale. Save raw captures.
5. Verify envelope/trigger fabric logic (rectify + leaky integrator) fires on knocks and stays quiet at rest; record thresholds.
6. Tap harder in controlled steps and watch for flat-topping at codes 0 and 4095: clipping at the clamp is expected for hard knocks and is the protection working, not a fault.

E. Clamp abuse test (bounded, bench supply only - unfabricated caveat)#

This test intentionally provokes the protection path. Run it on a current-limited bench supply, not on a host board, and accept that it is a prototype-risk experiment: no bench result yet exists showing the clamp network's real strike behavior, and piezo discs can deliver tens of volts open-circuit.

1. Scope the PIEZO node (10x probe) while striking the coupled surface progressively harder. The node must clamp near -V_F and 3.3 V + V_F (about -0.3 to -0.5 V and +3.6 to +3.8 V depending on strike current per the BAT54S V_F table). Excursions far beyond that mean D1 is not doing its job - stop.
2. Watch the 3.3 V rail during positive strikes: D1 pumps charge into the rail, and with only ~1.1 uF on board a large strike can lift a weakly loaded rail. Record any lift; if it is material, note a design action (bleed load or larger rail capacitance) before host use.
3. Confirm normal streaming resumes immediately after each strike and the quiescent code returns to mid-scale (a shifted rest code after abuse suggests a damaged divider resistor or ADC input).
4. Do not exceed hand-strike energy. Hammer blows, drop tests, and sustained overdrive are outside this prototype's evidence base; the 600 mA / <10 ms non-repetitive diode limit is real.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The signal chain is small but complete and each element carries real weight: the 1 MOhm trio gives the charge-source disc a mid-scale DC home at negligible standing current, the BAT54S (wired per its verified series pinout) turns a disc's worst habit into a bounded rail event, the pull-up on ~CS keeps the registerless ADC quiet until the host is real, and the decoupling meets the ADS7042's explicit reference-capacitance requirement. The interface facts (16-clock read-only frame, two leading zeros, calibration frames) were verified against the TI datasheet and match the schematic's annotations. The principal open risks are physical, not schematic: no layout exists (the AVDD reference decoupling placement and the high-impedance PIEZO node routing both matter), the disc itself is an uncharacterized TBD part, the clamp's real strike behavior and rail-pump magnitude have never been observed, and the LF-corner estimate is disc-dependent. Until a fabricated board passes Sections 9.A-9.D (and 9.E deliberately), every number here remains a target.