← AXS-028

Circuit review & bench-test guide

AXS-028 — ICS-43434 I2S microphone PMOD module

Document purpose#

This document explains the axs-028-ics43434 PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, the shared PMOD conventions in ../../pmod-common/PMOD-SPEC-NOTES.md, and the TDK InvenSense ICS-43434 datasheet cited in section 6.

This board is a schematic-complete prototype. It has NOT been laid out, fabricated, assembled, or bench-verified. Repository status: schematic generated, ERC clean (0 errors / 0 warnings), netlist reviewed; PCB layout not started. Every frequency, level, and timing figure below is a design target computed from the schematic and the datasheet — evidence to verify on the first article, not proof that a board works.

1. What the board does#

A TDK InvenSense ICS-43434 digital MEMS microphone with a standard 24-bit I2S output. The host is the I2S controller: it generates SCK (bit clock) and WS (word select) and deserializes 24-bit two's-complement samples. The mic's L/R pin, strapped by JP1, chooses which WS half-frame (stereo slot) this mic drives; a second module strapped to the other slot shares the same three wires for a stereo pair. This is the platform's first streaming-audio lesson (L4): level meter, FIR filter, and FFT display follow in fabric.

Functional block diagram#

                    3V3 ────────┬───────────────┐
                                |               |
                           C1 100nF      U1 ICS-43434
                                |        (I2S MEMS mic,
 PMOD J1                       GND        bottom port)
 pin 1  WS   ─────────────────────────────> WS   (word select, = SCK/64)
 pin 4  SCK  ─────────────────────────────> SCK  (bit clock, host-driven)
 pin 3  SD   <── R1 100R ── MIC_SD ──────── SD   (driven only in this
                    |                            mic's slot, else Hi-Z)
                R2 100k
                    |            JP1 L/R strap:
                   GND             1-2 GND (default) = left  = WS-low slot
                                   2-3 3V3           = right = WS-high slot

2. Safety and scope boundaries#

• 3.3 V only, from a PMOD host socket or a bench 3.3 V supply with the current limit at or below 20 mA. Expected draw is about 0.5 mA.
• The mic is a bottom-port MEMS device: never poke, vacuum, blow compressed air into, or wash over the port hole. No ultrasonic cleaning. Water must not reach the port during any board wash (datasheet handling rules).
• SCK and WS are host-driven; SD is module-driven through R1. Do not configure the host SD pin as an output.
• Do not drive SCK/WS while VDD is absent: the datasheet warns this continuously turns on ESD protection diodes and may affect long-term reliability. Power first, then clock.
• WS must be synchronous to SCK (exactly SCK/64) — generate both in the same fabric clock domain; a free-running function generator pair cannot satisfy the frame relationship.
• A working audio capture is not an acoustic calibration and no EMC/ESD/environmental claim follows from it.

3. Power and signal path#

1. 3V3 arrives on J1 pins 6/12, GND on 5/11. C1 (100 nF) decouples U1 VDD — the datasheet's strongly recommended 0.1 uF ceramic, to be placed tight to the part at layout.
2. On power-up the mic starts within 20 ms once clocks run. If SCK falls below about 200 kHz the mic enters standby; below an f_s of 3.125 kHz (WS) it sleeps at about 12 uA with SD high-impedance.
3. The host drives SCK and WS. The I2S frame is fixed: 64 SCK cycles per WS stereo frame (32 per half-frame), WS low = left slot, WS high = right slot. Sample rate f_s = WS frequency = f_SCK / 64.
4. With L/R strapped to GND (JP1 1-2, default = left), the mic outputs its 24-bit two's-complement word, MSB first, in the WS-LOW half-frame, with the MSB delayed one SCK from the WS falling edge (standard I2S). SD data transitions on SCK falling edges (valid within t_SDV = 75 ns); the host latches on SCK rising edges.
5. SD tri-states immediately after the LSB (24th bit) of its slot and stays Hi-Z through the remaining 8 cycles of the slot and the entire other half-frame. R2 (100 kΩ to GND) discharges the floating line so undriven bits read 0 — exactly the pull-down the datasheet recommends for shared SD lines.
6. R1 (100 Ω) is series protection on the mic-driven SD line, per the sensor-line rule for module-driven pins.

Why the frame must be exactly 64 SCK#

The datasheet is explicit: "There must be 64 SCK cycles in each WS stereo frame." A 32-cycle mono frame or a 48-cycle frame is not a supported format — the internal decimator derives its sample timing from this ratio. Hosts with configurable I2S blocks must be pinned to 32-bit slots, two slots per frame, 24 valid bits per slot.

4. Interfaces#

PMOD Type 7 (I2S) per Digilent Pmod spec 1.2.0: pin 1 WS (LRCLK), pin 2 NC (that is the DAC-data slot, unused by a microphone), pin 3 SD (ADC data), pin 4 SCK (BCLK). Pin 1 is the upper-row rightmost pin viewed from the module top with the connector toward you (PMOD-SPEC-NOTES).

No dedicated test points exist yet — the PCB is not laid out. Probing is at J1 pins and component pads.

5. Component-by-component review#

Every reference designator in the generator is covered.

6. Datasheet summary and design interpretation#

Datasheet actually fetched and read for this review (retrieved 2026-07-14): TDK InvenSense ICS-43434, document DS-000069, revision 1.2 (08/29/2016) — fetched from the Adafruit mirror of the official PDF at invensense.tdk.com (the tdk.com fetch returned a navigation shell at review time). One search result during this review described the ICS-43434 as obsolete — that claim is UNVERIFIED here; check TDK/distributor lifecycle status before layout.

7. Expected values before bench testing#

All values are design targets from the schematic and datasheet. Standard demo point: f_s = 48 kHz, SCK = 3.072 MHz.

8. Manual schematic and assembly review checklist#

• Verify U1 orientation (pin 1 = WS per the datasheet pin configuration; terminal side down) and that the PCB port hole (>= 0.5 mm recommended diameter) aligns with the package sound port, clear of paste, pour, and soldermask web (layout item; land pattern is 1:1 per the datasheet).
• Confirm JP1 is bridged 1-2 (L/R = GND = left) and not double-bridged and not open.
• Confirm C1 is X7R and placed tight to U1 VDD at layout, connection on a single layer without vias (datasheet layout guidance).
• Measure R1 = 100 Ω and R2 = 100 kΩ in circuit (SD-to-GND reads about 100 kΩ unpowered).
• Verify J1 pin-1 orientation and the Type 7 pin assignment (WS on 1, SD on 3, SCK on 4 — pin 2 stays NC for the DAC slot).
• Fix the "SCK 0.5–3.6 MHz" text in the README/schematic note to the datasheet-derived 0.4–3.3 MHz (finding, section 6).
• Check ICS-43434 lifecycle/stock status (obsolescence flag, section 6).

9. Ordered bench-test procedure#

Bench context: either (a) a PMOD host — AruviX ECP5 rev-A or any 3.3 V Digilent-compatible PMOD socket — generating SCK/WS in fabric, with a logic analyzer (>= 25 MS/s) and scope, or (b) a bench 3.3 V current-limited supply plus an FPGA/MCU I2S controller as the clock source (SCK and WS must be frame-locked; bench generators cannot substitute) and DMM/scope/logic analyzer. Stop at the first abnormal result.

A. Unpowered inspection and resistance#

1. Complete the checklist in section 8.
2. Measure 3V3-to-GND resistance both polarities; investigate a hard short.
3. SD-to-GND should read about 100 kΩ (R2); SD-to-3V3 open.

B. First power, no clocks#

1. Apply 3.3 V, current limit 20 mA. Do NOT drive SCK/WS yet (and never drive them before VDD — ESD-diode rule).
2. Record supply current; expect the mic to settle into standby/sleep territory (tens of uA). Milliamps mean a short or damaged part.
3. SD must read 0 V (R2 pull-down, output Hi-Z).

C. Clock bring-up#

1. Start the host I2S controller: SCK = 3.072 MHz, WS = 48 kHz, 50% duty, WS transitions aligned to SCK falling edges. Wait 20 ms (start-up spec).
2. Scope SCK and WS at J1: verify frequency, levels, duty, and that WS is exactly SCK/64 (trigger on WS, count SCK cycles per WS period: 64).
3. Record supply current: expect about 490 uA (high-performance mode).

D. I2S framing capture (PMOD Type 7-style verification)#

Capture SCK, WS, and SD together on a logic analyzer at >= 25 MS/s (>= 8x oversample of SCK). One correct stereo frame with JP1 default (L/R = GND = left = WS-low slot) looks like this:

        |<---------------- one WS frame = 64 SCK ---------------->|
WS   ___                                 ________________________
        \_______________________________/                        \____
         left slot (32 SCK)              right slot (32 SCK)

SCK  ..|_|-|_|-|_|-|_|-| ... |_|-|_|-|..|_|-|_|-| ...      |_|-|_|..
         1   2   3          24  25...32   1   2  ...  32   (cycle #)

SD   ---. .---.---.---.     .---.                                  .--
     Z  |X|B23|B22|B21| ... |B0 | Z Z Z Z 0 0 0 0 0 0 0 0 0 0 0 0 |X
     ---' '---'---'---' ... '---'----------------------------------'--
         ^   ^                  ^        ^
         |   MSB (B23) is one   |        unused right slot: Hi-Z,
         |   SCK after the WS   |        read as 0 through R2
         |   falling edge       LSB (B0) at cycle 25; SD tri-states
         |   (standard I2S)     immediately after — cycles 26-32
         WS falling edge        of the slot also read 0

Verify each property explicitly:

1. Frame length: exactly 64 SCK rising edges per WS period; WS duty 50% (32 low / 32 high).
2. Slot ownership: SD is driven only while WS is LOW (left slot). If data appears in the WS-high slot instead, JP1 is strapped 2-3 (right) or WS polarity is inverted at the host.
3. I2S alignment: the MSB appears one SCK after the WS falling edge — not zero (left-justified would be a host misconfiguration, and the mic never produces it).
4. Word format: 24 data bits, MSB first, two's complement, in a 32-SCK slot; slot bits 26–32 read 0.
5. Drive edge: SD transitions follow SCK FALLING edges (valid within 75 ns); the host must sample on SCK rising. On a fast scope, confirm the transition sits in the falling-edge window.
6. Tri-state/idle behavior: after the LSB, SD releases within 76 ns. With R1 (100 Ω) + R2 (100 kΩ) and about 10–20 pF of trace/probe load the release shows as a fast decay to 0 V (time constant about 1–2 us dominated by probe capacitance — a brief soft ramp at the hand-off is normal and is the visible signature of tri-state, not a fault). The entire right slot must read 0.
7. Sample values: in a quiet room, decoded left-slot words hover near zero (small positive/negative values — the 24 Hz internal HPF removes DC). All-zero exactly usually means the mic is not driving and R2 is being read; check MIC_SD on the U1 side of R1 to distinguish.

E. Rate sweep and mode behavior#

1. Legal-range sweep: run f_s = 24 kHz (SCK 1.536 MHz), 32 kHz (2.048 MHz), 44.1 kHz (2.8224 MHz), 48 kHz (3.072 MHz), 51.6 kHz max (3.302 MHz — at the 303 ns t_SCP limit; skip if the host cannot make a clean clock). Frames must stay valid at each point.
2. Low-power mode: f_s = 16 kHz (SCK 1.024 MHz) — inside the 6.25–18.75 kHz low-power window. Supply current should drop toward 230 uA.
3. Sleep/wake: stop both clocks (pull them to ground per the datasheet recommendation — parking WS high draws current through its internal pull-down). After about 1 s confirm current near 12 uA and SD at 0 V. Restart the clocks: data must resume 32768 SCK later (10.7 ms at 3.072 MHz) and be within 1 dB of final sensitivity within 20 ms.
4. Sequencing check: confirm the host never emits SCK/WS before module power (scope the bring-up once).

F. Acoustic smoke test in fabric#

1. Run the i2s_rx core at 48 kHz; stream decoded 24-bit samples to a level meter or UART dump.
2. Silence: samples near zero, noise floor on the order of -90 dBFS(A).
3. Whistle an approximately steady 1–2 kHz tone at 30 cm: a clean sine at that frequency, well above the noise floor. Speech at normal effort lands around -55 dBFS peaks (order-of-magnitude only — bench SPL is uncalibrated).
4. Loud transient (clap): peaks rise sharply but must not wrap or stick — two's-complement sign handling in the deserializer is the usual bug (a clap that produces full-scale negative "spikes" on positive pressure means sign-extension is wrong in fabric, not a board fault).
5. Stereo exercise (two modules): strap the second module 2-3 (VDD = right), tie SD lines together at the host socket pair. Verify left and right words interleave correctly and neither module drives the other's slot (scope for contention at slot hand-off; note both modules then carry an R2, halving the pull-down to 50 kΩ — still fine).

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The module matches the ICS-43434 datasheet's reference application almost exactly: single 100 nF bypass, the recommended 100 kΩ SD pull-down (R2), the L/R strap for stereo pairing, plus the platform's 100 Ω series protection on the module-driven line. The Type 7 pin map (WS/SD/SCK on pins 1/3/4, pin 2 reserved for DAC data) conforms to the corrected PMOD-SPEC-NOTES assignment. Findings: (1) the documented SCK range "0.5–3.6 MHz" overstates the datasheet limit — t_SCP min 303 ns caps SCK at 3.30 MHz; correct the README/schematic note and keep 48 kHz/3.072 MHz as the design point. (2) The part's lifecycle status is uncertain (an obsolescence flag surfaced during this review, unverified) — confirm availability before layout, with the INMP441 already named in the catalog as the alternative class. (3) SD output levels are V_OH >= 0.65 x VDD / V_OL <= 0.35 x VDD, weaker than full-rail CMOS — choose the host input standard and any input hysteresis accordingly. The framing contract (64 SCK per frame, 24-in-32 MSB-first, one-SCK delay, WS-low = left, tri-state after LSB) is fully testable with a logic analyzer using section 9.D, and nothing is bench-verified yet — every number above is a first-article target.