← AXS-025

Circuit review & bench-test guide

AXS-025 — LD2410C mmWave presence carrier PMOD module

Document purpose#

This document explains the axs-025-mmwave carrier at component level and turns the design evidence into a manual-review and bench-test plan. It is based on generate_design.py, the generated schematic, the README, and the official Hi-Link HLK-LD2410C user manual.

The board is an unfabricated prototype: schematic generated, ERC clean (0/0), netlist reviewed, no PCB layout, no fabricated board, no BOM export, no bench results. The J2 header MPN is TBD:.

1. What the board does#

The carrier adapts a Hi-Link LD2410C 24 GHz FMCW presence radar to a PMOD Type 3 (UART) socket, with the radar's presence GPIO (OUT) added on PMOD pin 1. Two abstraction levels: OUT is a plain high-when-present GPIO usable on day one; the UART carries the LD2410 binary protocol at 256000 baud (command/ack framing, per-gate energy values, engineering mode). The carrier is 3.3 V-only: J2 VCC is wired to the PMOD 3V3 rail — see the supply conflict in section 4.2.

Functional block diagram#

PMOD host (ECP5) J1                              LD2410C (plug-in, J2 1x5 header)
  pin 1 PRESENCE <── R1 100 Ω ──────────────────  OUT (high = presence)
  pin 2 TXD ────────────────────────────────────> RX (module receive)
  pin 3 RXD <── R2 100 Ω ───────────────────────  TX (module transmit, LD_TX)
  pins 6/12 3V3 ──┬── C1 100 nF ─┬── C2 10 µF ──> VCC   (conflict: manual says 5 V)
  pins 5/11 GND ──┴──────────────┴──────────────  GND

2. Safety and scope boundaries#

• The LD2410C is a 24–24.25 GHz ISM-band transmitter. Emission levels are designed for FCC/CE limits, but the assembled system is not certified; do not treat carrier bring-up as regulatory evidence.
• Bluetooth is enabled by default on the LD2410C and the radar is configurable over the air (default password HiLink). Treat an exposed bench unit as world-writable and re-verify parameters before trusting results.
• Keep the antenna face clear: no copper, hands, or metal within the sensing cone during quantitative tests; movement behind the module can also be detected via the back lobe (manufacturer note).
• Use a current-limited 3V3-capable host or supply; the module averages ~79 mA with ~130 mA peaks (manual Fig. 11), which is a meaningful load on a PMOD 3V3 rail — verify the host's rail budget.

3. Power and control sequence (design intent)#

1. Host powers the PMOD; 3V3 reaches J2 VCC through the carrier plane; C1/C2 supply chirp-current peaks.
2. The module boots, starts radiating, and streams periodic data frames at 256000 8N1 immediately; OUT asserts high when presence is detected.
3. Host TXD drives module RX directly (host-driven, no series resistor); module TX and OUT return through R2 and R1 (100 Ω each).
4. There is no reset or enable line: power-cycle is the only hardware reset.

4. Plug-in module verification (read before first power)#

Mandatory section. Three separate checks below; two of them are known conflicts with the official manual, not just theoretical clone variation.

4.1 Do-not-fit-LD2410 check (and the LD2410C's own rating)#

The carrier README asserts the LD2410C "accepts a 3.3 V supply" while the plain LD2410 wants 5 V and must not be fitted. The plain-LD2410 prohibition is correct and stands: never fit an LD2410 or LD2410B — there is no 5 V anywhere on this carrier and those modules specify 5 V. Identify the module by its silkscreen model marking (HLK-LD2410C-Vx.x) before soldering.

4.2 Supply-voltage conflict (unresolved design risk)#

The official HLK-LD2410C manual V1.00 does not support the 3.3 V premise: its pin table gives VCC as "Power input 5~12 V (advise 5 V)" and the electrical table says "DC 5V, power supply capacity > 200 mA". Some vendor listings claim 3.3 V tolerance for specific LD2410C builds, but that is not in the manufacturer document reviewed here. Until resolved:

• Treat "runs correctly at 3.3 V" as an open question to be answered on the bench with a sacrificial module, powered from a current-limited supply, before committing the carrier design.
• Likely failure mode at 3.3 V is undervoltage misbehavior (brownout, reduced range, resets during chirps) rather than damage, but that is an expectation, not a datasheet fact.
• If 3.3 V operation cannot be demonstrated, the carrier needs a redesign (external 5 V entry like AXS-024/044/045, with level care on RX).

4.3 Pin order and pitch (two hard mismatches to fix before fab)#

• Numbering direction: the manual's pin table is 1 TX, 2 RX, 3 OUT, 4 GND, 5 VCC (module silkscreen reads TX RX OUT GND VCC). The carrier schematic assumes 1 VCC, 2 GND, 3 OUT, 4 RX, 5 TX — the exact reverse. The physical row is the same; whether it mates correctly depends entirely on which end becomes "pin 1" after the header is soldered and the module is plugged in. A reversed mating puts VCC on TX and TX on VCC. Resolution: after layout, the carrier silkscreen must label each J2 position with the module's own signal names, and the bench check below must be run on every assembly.
• Pitch: the manual specifies the module's five pin holes at 2.54 mm pitch, 0.9 mm diameter. The carrier J2 footprint is a 1.27 mm 1×5 header (PinHeader_1x05_P1.27mm_Vertical). These cannot mate. The footprint must be changed to 2.54 mm before fab. (Clone boards may differ — measure the purchased module, but the official drawing says 2.54 mm.)

Bench check before first power, module in hand:

1. Read the module silkscreen next to its five holes; write down the order.
2. Solder the header, plug into the carrier (unpowered), and buzz from the module's VCC hole to the PMOD 3V3 pins, and from the module's GND hole to PMOD GND. Both must be correct before applying power.
3. Buzz module TX to the R2 side (LD_TX) and OUT to the R1 side (LD_OUT).

4.4 Plug-in key specifications (HLK-LD2410C manual V1.00, 2022-11-07)#

5. Component-by-component review#

#FLG01/#FLG02 are ERC power flags, not physical parts.

Host TXD → module RX is direct (host-driven line, consistent with the series convention used across this board family).

6. Datasheet summary and design interpretation#

Official reference: HLK-LD2410C user manual V1.00 (hlktech.net), vendor site hlktech.net. Hi-Link also publishes a separate "LD2410C Serial Port Communication Protocol" document for the frame formats; obtain the revision matching the purchased firmware.

7. Expected values before bench testing#

8. Manual schematic and assembly review checklist#

• Resolve the supply question (4.2) with a sacrificial module before layout; document the answer in the repository.
• Change the J2 footprint to 2.54 mm pitch (4.3) and re-run ERC/DRC.
• Add module-signal-name silkscreen at J2 to kill the reversal ambiguity.
• Pin J1/J2 TBD: MPNs before BOM release.
• After layout: antenna face keep-out (no copper under/in front of the module), C1/C2 adjacent to the socket, verify PMOD pin-1 orientation.
• Confirm R1/R2 sit in the module-driven lines (OUT, TX), not the host TXD.

9. Ordered bench-test procedure#

Stop at the first abnormal result.

A. Module qualification (before any carrier use)#

1. Power a bare LD2410C from a current-limited bench supply at 5.0 V through jumper wires; confirm UART frames and OUT behavior (baseline).
2. Reduce supply in steps 4.5 → 4.0 → 3.6 → 3.3 V, watching current, frame integrity, and detection range. Record the lowest reliable voltage. This answers section 4.2. If 3.3 V fails, stop: the carrier needs redesign.

B. Unpowered carrier checks#

1. Complete section 4.3 buzz-out (VCC/GND/TX/OUT to the right nets).
2. Resistance 3V3-to-GND at the PMOD plug; investigate a hard short.

C. First power and presence GPIO#

1. Attach to the host; power on; measure J2 VCC and module current.
2. With the room still, OUT should settle low; walk into the cone at 2 m — OUT high within ~1 s; leave — OUT drops only after the configured unmanned delay (default 5 s). Do not misread the delay as a fault.
3. Scope the 3V3 rail at C2 during operation; note droop.

D. UART protocol#

1. Capture LD_TX at 256000 8N1; verify the periodic data-frame headers and parse target state / moving and static distance and energy per the Hi-Link serial-protocol document.
2. Send a read-parameters command from the host through TXD and verify the ack frame — this proves the host-driven RX path.
3. Verify your ECP5 baud generator: 256000 from your fabric clock must land within ~2 %; log the actual divider error.

E. Behavior and interference#

1. Range-gate test: configure max gate to 2 (1.5 m); confirm a person at 3 m is ignored.
2. Bluetooth: confirm the module is visible in the HLKRadarTools app; change and restore one parameter; then decide whether to disable Bluetooth via the serial protocol for bench integrity, and record the choice.
3. Back-lobe test: movement behind the carrier; record whether it triggers (manufacturer warns it can).

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The signal architecture is sound — 3.3 V IO with series resistors on both module-driven lines and honest decoupling for chirp peaks. But this carrier currently rests on an assumption the manufacturer's own manual contradicts: the official HLK-LD2410C document specifies a 5 V supply and 2.54 mm pin holes, while the carrier feeds 3.3 V into a 1.27 mm footprint. Combined with the reversed pin-numbering convention, there are three release blockers: demonstrate (or abandon) 3.3 V operation on a real module, fix the J2 pitch, and disambiguate pin 1 on silkscreen. Until then, no board should be fabricated from this schematic.