← AXS-020

Circuit review & bench-test guide

AXS-020 — TLV493D 3D hall-effect sensor PMOD module

Document purpose#

This document explains the axs-020-tlv493d prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, and the manufacturer documents cited in Section 6.

The board is schematic-only: ERC is clean, but no PCB has been laid out and no board has been fabricated or assembled. There is no bench result of any kind. Every numeric value in this guide is a verification target taken from the design files or the manufacturer datasheets, not a measured result.

1. What the board does#

The board puts an Infineon TLV493D-A1B6 low-power 3D magnetic (Hall) sensor on the AruviX I2C PMOD template for a rotary-position lesson: a diametral magnet on a shaft spins above the SOT-23-6 package and the FPGA fabric computes the shaft angle as atan2(By, Bx), plus 3D field measurement and a CORDIC exercise. The sensor measures Bx/By/Bz up to ±130 mT with 12-bit resolution (0.098 mT/LSB) and includes a temperature channel.

The interface is minimal by design: the TLV493D has only SCL and SDA. There is no dedicated interrupt pin — when interrupt mode is enabled the sensor pulses SCL during bus idle — and there is no register-address pointer: reads always stream from read-register 0 upward, and a write transaction streams into write-registers 0–3. The I2C address is latched from the SDA level during power-up, which is the single most important bring-up quirk of this board (Section 3).

Functional block diagram#

PMOD host (3.3 V)
      │
      v
J1 PMOD plug (2x06)
  3/9  SCL  <──── JP2 ─── R2 4.7k ── 3V3   (SCL pull-up)
  4/10 SDA  <──── JP1 ─── R1 4.7k ── 3V3   (SDA pull-up)
  5/11 GND, 6/12 3V3
  1/2/7/8 NC (no interrupt pin exists on the sensor)
      │
      v
   U1 TLV493D-A1B6 (SOT-23-6)
      pin 4 VDD = 3V3 (C1 100n)
      pins 2/3/5 GND
      pin 1 SCL / /INT   (interrupt pulses multiplex onto SCL)
      pin 6 SDA / ADDR   (SDA level at power-up latches the I2C address)

2. Safety and scope boundaries#

• 3.3 V logic only, and tighter than usual: the TLV493D absolute maximum on VDD and on any pin is 3.5 V (operating range 2.8–3.5 V). A 3.3 V +5 % rail (3.465 V) fits; a "3.3 V" bench supply with overshoot, or any 5 V contact, can destroy the part. The datasheet's power-up envelope V_OUS = 3.0–3.5 V must not be exceeded at the end of power-up.
• Use a current-limited bench supply (3.3 V, ~50 mA limit). The datasheet asks the supply design to allow at least 10 mA for the sensor: average operating current peaks at 3.7 mA during each ~270 µs ADC burst even though the average in low-power modes is tens of µA.
• Absolute maximum magnetic field is 1 T; ordinary test magnets are safe, but the linear range is ±130 mT — angle math degrades if the magnet saturates the axes. ESD ratings are ±1.5 kV HBM: handle with normal ESD care.
• The datasheet specifies a fast supply ramp (t_PUP ≤ 10 µs) for a clean power-on; a slow bench ramp may leave the interface in an undefined state. The documented remedy is the I2C recovery/reset frame (Section 9.D) or a clean power cycle — plan for it rather than debugging ghosts.
• This guide validates a prototype schematic. Passing it is not EMC, safety, or environmental qualification, and no layout-dependent behavior can be checked before a PCB exists.

3. Power and control sequence#

1. 3V3 is applied on J1 pin 6/12; C1 (100 nF at VDD) charges. The supply should ramp fast (t_PUP ≤ 10 µs per datasheet Table 6) and settle inside 3.0–3.5 V. Power-up current draw I_DD-PUP is ~3.7 mA during the ramp.
2. Address latch: during power-up the power-mode-control unit interprets the voltage on the ADDR pin — which is the SDA pin — as logical 0 or 1 and latches one of two I2C addresses (datasheet Section 2.1.1). On this board R1 pulls SDA to 3V3, so with a quiet bus the sensor latches SDA = high and answers at 7-bit address 0x5E (write 0xBC, read 0xBD). If anything holds SDA low at that instant — another device mid-transaction on a chained bus, a host actively driving, a scope ground bounce — the sensor latches the alternate address 0x1F (write 0x3E, read 0x3F) instead. (Address pair per the Infineon TLV493D-A1B6 user manual and Infineon's reference library; see Section 6.)
3. After power-up the sensor is in power-down mode (7 nA typical), all measurement off. Registers can be read/written but no field data is produced yet.
4. To measure, the host must write a 4-byte configuration (write-registers 0–3) that: copies three factory-setting bit fields from read-registers 7–9, selects the mode bits (FAST/LOW in MOD1, LP period and temperature enable in MOD2), and sets the parity bit so the total number of 1s in all 32 written bits is odd. A parity error makes the sensor ignore the configuration.
5. In master-controlled mode (FAST = 1, LOW = 1, LP period = 1) a measurement of Bx, By, Bz (plus temperature unless disabled) runs after each readout; in low-power (100 Hz) or ultra-low-power (10 Hz) modes it runs on the internal oscillator, optionally pulsing /INT on SCL for 1.5 µs at end of conversion — leave interrupt off unless the host FSM tolerates pulses on the clock line.
6. Reads always start at read-register 0: the host issues SAD+R and streams 7 bytes (Bx/By/Bz/Temp/flags) or 10 bytes (adds the factory registers). The sensor has no shadow buffers, so a read must not straddle a running conversion; check the CH bits (= 0) to confirm frame consistency.

There is no regulator or level shifter; #FLG01/#FLG02 are ERC-only power- flag artifacts with no physical part.

4. Interfaces#

PMOD pin map (Type 6 extended, J1 = 2x06 right-angle header)#

Pins 9/10 repeat the bus for daisy-chaining. No interrupt pin is wired because the sensor has none.

Jumpers#

Test points#

None are defined in the schematic. Probe at J1 pins; consider adding SDA/SCL/3V3 test points at layout, since power-up bus state matters more on this module than on most.

5. Component-by-component review#

Every reference designator in generate_design.py is covered.

Key U1 datasheet parameters (TLV493D-A1B6, Rev 1.1, 2019-04-09)#

6. Datasheet summary and design interpretation#

Official references: TLV493D-A1B6 datasheet (Infineon), TLV493D-A1B6 user manual v1.03 (Mouser-hosted), Infineon TLV493D-A1B6 reference library (GitHub), Yageo RC thick-film resistors. Check the latest revisions before procurement.

7. Expected values before bench testing#

All values are targets from the schematic and the documents above; none has been measured on hardware.

8. Manual schematic and assembly review checklist#

• Confirm U1 orientation on the SOT-23-6 footprint (pin 1 = SCL//INT).
• Verify VDD is pin 4 and all of pins 2/3/5 are grounded (the schematic labels each explicitly — check the netlist carried them).
• Confirm C1 lands electrically close to U1 pin 4 (layout stage).
• Confirm JP1/JP2 bridged for a single-module bench; for a chain, exactly one module keeps its pull-ups and that module's power-up SDA state governs every TLV493D's address latch on the bus.
• Verify supply source: 3.3 V nominal with overshoot verified < 3.5 V on a scope before the first sensor is attached.
• Confirm nothing is fitted for #FLG01/#FLG02 (schematic artifacts).
• Host-side review: the I2C master must be quiet (no transactions, SDA released) from before VDD ramp until first access, and must tolerate the absence of a register-pointer protocol (raw stream reads/writes).
• After layout (future): magnet-over-sensor target on silkscreen; keep the sensor away from the header current loop.

9. Ordered bench-test procedure#

Stop at the first abnormal result. PMOD host at 3.3 V or a current-limited 3.3 V bench supply on J1 pins 6/12 and 5/11. Verify supply overshoot < 3.5 V into a dummy load before ever connecting the module.

A. Unpowered inspection and resistance tests#

1. Complete the Section 8 checklist under magnification.
2. Measure 3V3-to-GND in both polarities; investigate any hard short.
3. Pull-up jumper verification (fitted default): SDA (J1 pin 4) to 3V3 (pin 6) ≈ 4.7 kΩ; SCL (pin 3) to 3V3 ≈ 4.7 kΩ.
4. If chaining, cut JP1/JP2 and re-measure: both go open; confirm the chain still has exactly one 4.7 kΩ per line, and note that the surviving pull-up now defines this sensor's power-up address too.

B. First power, idle current, bus idle levels#

1. Apply 3.3 V (50 mA limit) with the bus completely idle — host attached but not transacting, SDA released high.
2. Expect essentially zero steady current (power-down mode, 7 nA typical; below most bench meters). A steady mA-range draw means a fault.
3. Probe SDA and SCL: both at 3.3 V.

C. Address-ACK scan#

1. Scan the bus at 100 kHz. Expect an ACK at exactly 0x5E and nowhere else from this module.
2. An ACK at 0x1F instead means the address mis-latched: something held SDA low during power-up. Go to step D.

D. Address-latch quirk: deliberate mis-latch and recovery#

This step characterizes the board's one real trap so it is recognized later.

1. Power off. Force SDA low (host driving low, or a temporary 1 kΩ to GND stronger than R1). Power on, release SDA, rescan: the sensor should now ACK at 0x1F and not at 0x5E — demonstrating that bus traffic during power-up re-addresses the part.
2. Recovery, option 1 (preferred): power-cycle with a quiet bus (SDA high through R1). Rescan: back at 0x5E.
3. Recovery, option 2 (documented reset frame, per Infineon's library): general-call write — START, address byte 0x00, data byte 0x00, STOP — re-initializes the sensor to address 0x5E (data 0xFF selects 0x1F). Also useful when a host reset stranded the sensor mid-transaction.
4. Rule derived for AruviX hosts: never start I2C traffic until 3V3 is stable, and after any brownout, either power-cycle or send the reset frame before trusting the address.

E. First transaction: factory read, config write, first frame#

The sensor has no register pointer: a read streams from read-register 0.

1. Read 10 bytes: START, 0xBD (SAD+R for 0x5E), read 10 bytes, NACK, STOP. Bytes 0–6 are the measurement frame; bytes 7–9 are factory settings. In power-down mode the field bytes hold the reset/default frame — the interesting content right now is bytes 7–9. Save them.
2. Build the 4-byte config (write-registers 0–3):

• WB0 = 0x00 (reserved).
• WB1: bit7 = parity P; bits6:5 = IICaddr (leave 00); bits4:3 = copy of read-reg 7 bits 4:3; bit2 = INT enable (0 — interrupts pulse SCL, leave off); bit1 = FAST; bit0 = LOW.
• WB2 = copy of read-reg 8 (all 8 bits).
• WB3: bit7 = T (1 disables temperature); bit6 = LP period (1 = 100 Hz, 0 = 10 Hz); bit5 = parity-test enable; bits4:0 = copy of read-reg 9 bits 4:0.
• For master-controlled mode set FAST = 1, LOW = 1, LP period = 1; for low-power 100 Hz set FAST = 0, LOW = 1, LP period = 1.
• Parity: set P so the total number of 1 bits across WB0..WB3 is odd (compute even parity with P pre-set to 1, then write the result back into P — the Infineon library algorithm).

1. Write: START, 0xBC (SAD+W), WB0, WB1, WB2, WB3, STOP. Expect ACKs on all five bytes.
2. Wait ≥10 ms, then read 7 bytes (SAD+R, 7 bytes): parse

• Bx = (byte0 << 4) | (byte4 >> 4), By = (byte1 << 4) | (byte4 & 0x0F), Bz = (byte2 << 4) | (byte5 & 0x0F) — each a 12-bit two's-complement value, × 0.098 mT/LSB;
• byte3: bits3:2 = FRM frame counter, bits1:0 = CH channel bits;
• byte5 bit4 = power-down/conversion-complete flag;
• temperature = ((byte3 & 0xF0) << 4) | byte6, (value − offset) × 1.1 °C/LSB with ≈340 LSB at 25 °C.

1. Expected at rest (no magnet): each axis within the ±1 mT offset band (≈ ±10 LSB) — i.e. near zero; Earth's field (~25–65 µT) is below one LSB (98 µT) and may show only as a stable ±1-count bias. CH must be 0 (all channels from the same frame) and FRM must increment modulo 4 between successive reads — a frozen FRM means the config write was rejected (almost always parity or missing factory bits).

F. Magnet and rotary-position test#

1. Bring a small magnet toward each package face: the matching axis must respond with tens to hundreds of LSB and correct sign per the datasheet's field-direction figure (positive = south pole facing the element).
2. Confirm no axis saturates (±2047 LSB rails) at the intended magnet working distance; if it does, increase distance — angle accuracy needs the linear ±130 mT region.
3. Mount a diametral magnet on a shaft above the package. Rotate slowly: atan2(By, Bx) must sweep monotonically through 360° per revolution, and Bz should stay roughly constant. Record the amplitude ratio |Bx|/|By| (X/Y matching is ±5 % typ drift; gross mismatch means geometry is off).

G. Modes, rates, and current#

1. In low-power mode (100 Hz), verify ~100 frames/s of fresh FRM counts and an average current of order 80 µA (65 µA with temperature disabled via WB3 bit7 — expect roughly −25 %).
2. In ultra-low-power (10 Hz), verify ~10 frames/s and ~10 µA.
3. Optionally enable INT (WB1 bit2) and scope SCL for the 1.5 µs end-of- conversion low pulse — only with the host master idled, and disable it again afterward.
4. Return to power-down (FAST = 0, LOW = 0) and confirm current collapses to the meter floor.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic is intentionally minimal and matches the datasheet application circuit: one decoupling capacitor, two pull-ups behind chain jumpers, and nothing else. Its correctness therefore lives almost entirely in procedure: the power-up address latch means the pull-ups are not just bus components but configuration straps, and the no-register-pointer protocol plus the odd-parity config write make the first transaction the real test. The principal open risks are the tight 3.5 V absolute maximum against bench supply overshoot, address mis-latch behavior in chained configurations (only one module's pull-ups survive, and power-up bus quietness becomes a system property), the unfetched user manual (bitmap verified against Infineon's reference library, to be re-checked), and — as with every board in this series — the fact that no PCB exists yet, so every number above is a target, not a result.