← AXS-018

Circuit review & bench-test guide

AXS-018 — ICM-20602 high-rate 6-axis IMU PMOD module

Document purpose#

This document explains the axs-018-icm20602 module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on generate_design.py, README.md, and the ERC evidence in reports/.

This board has never been fabricated or assembled. The schematic is generated and ERC clean (0/0), and the netlist has been reviewed, but the PCB layout has not been started — there are no gerbers, no renders, and no physical board. Every number in this guide is a design target or a datasheet expectation to verify, not a measured result. Layout-dependent items — decoupling placement, REGOUT loop, high-rate SPI signal integrity, and the mechanical mounting stiffness that matters for a MEMS IMU — cannot be reviewed yet and are flagged below.

1. What the board does#

AXS-018 is a PMOD Type 2A (expanded SPI) peripheral carrying a TDK InvenSense ICM-20602 6-axis IMU (3-axis gyro + 3-axis accelerometer, LGA-16 3×3 mm). The host FPGA or MCU supplies 3.3 V through the PMOD plug and talks 4-wire SPI (mode 0 or 3, up to 10 MHz). The part streams up to 32 kHz gyro-class samples through a 1008-byte FIFO with watermark interrupts on INT1 (PMOD pin 7). This is the AruviX high-rate streaming / DMA lesson: moving samples into fabric buffers faster than a polled register loop can.

Catalog substitution: the catalog originally listed the ICM-42688-P, which has no stock KiCad symbol/footprint; the ICM-20602 keeps the same high-rate-FIFO curriculum with stock assets. The ICM-20602's I2C mode is deliberately not used — a 10 kΩ pull-up keeps ~CS high so the part stays in SPI posture before the host configures its pins.

Functional block diagram#

PMOD plug J1 (2x6 right-angle)
  6/12: 3V3 ──┬────────┬────────┬────────┐
              C1 100n   C2 100n  C3 2.2u  R3 10k
              (VDD)     (VDDIO)  (bulk)      │
  1: CS_N ─────────────────────────────────┴──> U1 ~CS (5)
  2: MOSI ──────────────────────────────────────> U1 SDI (3)
  4: SCK  ──────────────────────────────────────> U1 SPC/SCLK (2)
  3: MISO <── R1 100R ── IMU_SDO ─────────────── U1 SDO (4)
  7: INT1 <── R2 100R ── IMU_INT1 ────────────── U1 INT (7-side)

  U1 supplies: VDD (16) + VDDIO (1) on 3V3, GND (9) to GND
  U1 FSYNC ── tied to GND (unused input)
  U1 REGOUT ── C4 100n ── GND   (internal LDO bypass)

2. Safety and scope boundaries#

• Electrically benign to the operator: 3.3 V, low mA. Hazards are to the part. Standard ESD handling; the datasheet carries the usual MEMS ESD caution.
• VDD/VDDIO operating range is 1.71–3.45 V; absolute maximum is 3.6 V. 3.3 V nominal leaves only ~0.15 V to the operating max and ~0.3 V to the absolute max — a 5 V PMOD socket or a mis-set supply destroys U1. Verify the rail before every first connection, and check the supply's actual output, not its dial.
• Never drive CS/SCLK/MOSI (or back-drive MISO/INT1) above VDDIO + 0.3 V, including while unpowered.
• Power-up with SCLK/~CS held low is not supported (datasheet): if it happens, a software reset via PWR_MGMT_1 is required before initialization.
• Bench handling will not hurt the MEMS (high shock rating), but do not hammer-test; gentle taps/rotations are sufficient to exercise it.
• Use a current-limited 3.3 V bench supply (≤ 50 mA is ample). Typical run current is a few mA (gyro + accel on).
• Passing WHO_AM_I and self-test is not a calibration or qualification claim.

3. Power and signal sequence#

1. The host (or bench supply) applies 3.3 V to PMOD pins 6/12, GND on 5/11. VDD (pin 16) and VDDIO (pin 1) are the same 3.3 V net; C1/C2/C3 charge.
2. The internal LDO regulates the analog core; its output is bypassed by C4 (100 nF) at REGOUT. C4 is not optional — it stabilizes the on-chip regulator that powers the MEMS front end.
3. R3 (10 kΩ) holds ~CS at 3.3 V while the host FPGA is unconfigured, keeping the part in SPI posture and deselected.
4. The device comes up in sleep mode (datasheet). The host must clear the SLEEP bit in PWR_MGMT_1 (0x6B) before any measurement; a software reset (PWR_MGMT_1 = 0x80) is the recommended first move to a known state.
5. The host reads WHO_AM_I (0x75) and expects 0x12 — the canonical first transaction (section 7).
6. The host configures gyro/accel full-scale (GYRO_CONFIG 0x1B, ACCEL_CONFIG 0x1C), sample rate, DLPF, and FIFO (FIFO_EN 0x23, USER_CTRL 0x6A), optionally enabling the FIFO watermark interrupt (INT_ENABLE 0x38, INT_PIN_CFG 0x37).
7. Samples stream into the FIFO; INT1 (push-pull) asserts on data-ready or watermark and passes through R2 to PMOD pin 7. The host burst-reads FIFO_R_W (0x74) using FIFO_COUNT (0x72/0x73) to size the read.

4. Interfaces#

SPI framing (datasheet Serial Interface section):

• 4-wire SPI, mode 0 (CPOL=0/CPHA=0) or mode 3 (CPOL=1/CPHA=1), MSB first, ≤ 10 MHz (register writes are limited to 1 MHz on some InvenSense parts — confirm; reads may run full rate). Start slow during bring-up.
• First byte: bit 7 = R/~W (1 = read), bits 6:0 = register address. Address auto-increments on multi-byte transactions while SCLK continues.
• ~CS low frames every transaction; raise it between register groups.

No dedicated test points; probe at J1 and the R1–R3 / C1–C4 pads. (Layout to-do: add probe pads and keep SCLK/MISO short for 10 MHz before fab.)

5. Component-by-component review#

5.1 Sensor and connector#

5.2 Decoupling and regulator bypass#

The board matches the datasheet's external-BOM list exactly: REGOUT 0.1 µF (C4), VDD 0.1 µF (C1) + 2.2 µF (C3), VDDIO 0.1 µF (C2). Layout rule when the PCB is done: C1/C2/C4 tight to their pins with a low-impedance ground return.

5.3 Series protection and strap#

FSYNC is tied to GND (unused input, per datasheet). RESV pin is left open (no-connect typed in the stock symbol, per datasheet). Power flags #FLG01 (3V3) / #FLG02 (GND) are ERC-only. Every reference designator is covered (U1, J1, C1–C4, R1–R3).

6. Datasheet summary and design interpretation#

Primary reference: ICM-20602 datasheet DS-000176 Rev 1.0 (TDK InvenSense). Check the revision before procurement.

Official reference: ICM-20602 datasheet DS-000176.

7. Expected values before bench testing#

None of these have ever been measured on this design — no board exists.

The canonical first read: WHO_AM_I over SPI#

1. (recommended) Software reset:  MOSI 0x6B, 0x80 ; wait ~100 ms.
2. Clear sleep:                   MOSI 0x6B, 0x01 (auto clock select, SLEEP=0).
3. Read WHO_AM_I:                 MOSI 0xF5 (0x80 read | 0x75), then 1 dummy byte.
   MISO byte -> expect 0x12.

Any answer other than 0x12 stops the bring-up. 0x00/0xFF = MISO dead (R1 open, SDO unsoldered, wrong pin, ~CS not asserted, or part in sleep with SCLK/~CS power-up violation); shifted values = wrong SPI mode or bit alignment or over 10 MHz on long leads.

REGOUT capacitor check#

C4 is the highest-leverage passive on the board. Before trusting any data, confirm ~1.8 V at the REGOUT node once powered and that C4 is populated and not a cold joint — an unstable REGOUT gives intermittent WHO_AM_I and noisy MEMS output that looks like a bad part.

FIFO smoke test (design intent)#

Configure FIFO for accel+gyro (FIFO_EN 0x23), reset and enable the FIFO (USER_CTRL 0x6A: FIFO_RST then FIFO_EN), let it fill briefly, read FIFO_COUNT (0x72/0x73) — it should grow at (samples × bytes/sample) — then burst-read FIFO_R_W (0x74) and confirm the byte count matches. This proves the streaming path the module exists to teach, before any high-rate soak.

Self-test summary#

Set the self-test bits in GYRO_CONFIG (0x1B) and ACCEL_CONFIG (0x1C), average output with self-test off then on, and compute ST response = (on − off) per axis. The part passes when each axis response falls within the min/max limits in the product-spec self-test tables. Run in normal power at a supported ODR with the board stationary; log the exact supply voltage.

8. Manual schematic and assembly review checklist#

Schematic/netlist items (reviewable now):

• U1 pin map: VDDIO=1, SCLK/SPC=2, SDI=3, SDO=4, ~CS=5, INT=7, GND=9, VDD=16; FSYNC to GND, REGOUT to C4, RESV open. Confirm MOSI→SDI(3), MISO←SDO(4) through R1 — a swapped SDI/SDO is the classic dead-WHO_AM_I cause.
• Confirm C4 sits on REGOUT (not on VDD) — a common copy-paste error.
• Re-run reports/erc.rpt after any regeneration; must stay 0/0.

Assembly items (for the eventual first article — none exists yet):

• LGA-16 orientation mark and reflow quality (X-ray or angled inspection — leadless pads hide opens); no trapped flux under the LGA.
• Confirm the 2.2 µF bulk orderable MPN (GRM188R61A225KE34D, TBD-confirm).
• Layout gate (cannot pass today): C1/C2/C4 tight to their pins, short 10 MHz SCLK/MISO, low-inductance ground, U1 on a supported (not cantilevered) region for a MEMS part, PMOD pin-1 vs a physical host socket.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, exact supply voltage, orientation fixture, SPI mode/clock, equipment, and operator. Two host contexts: standalone (current-limited 3.3 V bench supply + SPI adapter, phases B–E) and PMOD host (FPGA/MCU providing 3.3 V, phase F). Standalone first.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 assembly checklist under magnification.
2. DMM 3V3→GND (J1 pin 6→5), both polarities: no hard short.
3. ~CS (pin 1) → 3V3 (pin 6): ≈ 10 kΩ (R3).
4. MISO (pin 3) / INT1 (pin 7) → U1 pads: ≈ 100 Ω. MOSI/SCK → U1 3/2: ≈ 0 Ω.

B. Standalone first power (current-limited bench supply)#

1. Bench supply 3.3 V (measure it — abs max 3.6 V), current limit 20–50 mA, output off. Wire + to J1 pin 6, − to pin 5. Do not hold SCLK/~CS low through power-up.
2. Power on: no current-limit trip; sleep-mode current (low mA). Confirm ~1.8 V at REGOUT (C4) and ~CS idling at 3.3 V through R3.

C. Standalone SPI bring-up (adapter, still on bench supply)#

Use any 3.3 V SPI master. Configure mode 0 or 3, start at 1 MHz, MSB first, common ground.

1. Software reset + wake: PWR_MGMT_1 (0x6B) = 0x80, wait ~100 ms, then 0x01 (clear SLEEP).
2. WHO_AM_I: run the section 7 read → expect 0x12. Capture the first frame regardless of result.
3. Register write/readback: write GYRO_CONFIG (0x1B) = e.g. 0x18 (±2000 dps), read it back → proves MOSI framing both ways.
4. Static accel read: clear sleep, read ACCEL_XOUT..ZOUT — Z ≈ +1 g in the selected FS counts, X/Y ≈ 0. Rotate the board and watch the axes track.
5. Clock up: repeat WHO_AM_I at 5 then 10 MHz; confirm reads stay 0x12.

D. FIFO smoke test#

1. Configure sample rate/DLPF, FIFO_EN (0x23) for accel+gyro, reset+enable via USER_CTRL (0x6A).
2. Wait a known interval, read FIFO_COUNT (0x72/0x73), confirm it grew by samples × bytes/sample.
3. Burst-read FIFO_R_W (0x74); confirm the byte count and that samples are sane. Then enable the FIFO watermark interrupt and confirm INT1 (PMOD 7) asserts at the programmed threshold and clears on read (INT_STATUS 0x3A).

E. Self-test summary#

1. Board stationary, normal power, supported ODR. Average N samples with self-test off → baseline per axis (gyro + accel).
2. Set the ST bits (GYRO_CONFIG 0x1B, ACCEL_CONFIG 0x1C), settle, average N samples on → compute ST response = on − off per axis.
3. Compare each axis against the product-spec min/max self-test limits; pass = within range. Clear the ST bits. Repeat once; runs should agree. Log the exact supply voltage.

F. PMOD-host context (FPGA/MCU provides 3.3 V)#

1. Measure the host socket rail: must be 3.3 V (abs max 3.6 V). Confirm the I/O bank voltage.
2. Plug in with host unconfigured; verify ~CS reads 3.3 V at the module.
3. Reproduce the phase C/D ladder from the host: reset/wake → WHO_AM_I 0x12 → config → static accel → FIFO stream on INT1 watermark.
4. Scope the first host-driven frame; confirm mode and clock, and that ~CS is never held low through power-up.
5. High-rate soak (the module's purpose): stream at a high ODR through the FIFO for 30+ minutes; count FIFO overflows (INT_STATUS) and framing errors; re-read WHO_AM_I every N frames (stays 0x12). Zero overflow at the target rate is the streaming pass criterion.

G. Release-only tests#

Gyro/accel sensitivity and bias calibration against a rate table / precision fixture, temperature characterization, full 10 MHz signal-integrity margining on the real layout, vibration/mounting-resonance evaluation, and ESD belong to a separate qualification plan gated on a fabricated board.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic is a faithful minimal implementation of the ICM-20602 datasheet's application: both supplies on 3.3 V with the prescribed 0.1 µF + 2.2 µF VDD and 0.1 µF VDDIO decoupling, the REGOUT internal-LDO bypass (C4) present, FSYNC grounded, RESV open, ~CS defended by a 10 kΩ pull-up, and sensor-driven MISO and INT1 behind 100 Ω series resistors. The principal risks are that nothing physical exists yet — no layout, no board, no first-article data; the LGA-16's inspection difficulty; the 3.45 V operating / 3.6 V absolute-maximum rail with essentially no 5 V tolerance; the power-up-with-SCLK/~CS-low hazard that needs a software reset; and 10 MHz SPI signal integrity plus MEMS mounting placement, neither judgeable until a layout exists. The bring-up ladder — reset/wake, WHO_AM_I 0x12, REGOUT check, register readback, static accel, FIFO smoke test, self-test — is exactly the sequence the AruviX SPI-plus-FIFO streamer will need to reproduce.