← AXS-017

Circuit review & bench-test guide

AXS-017 — LSM6DSM 6-axis IMU PMOD module

Document purpose#

This document explains the axs-017-lsm6dsm prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the authoritative design sources in this directory: generate_design.py (the schematic generator), README.md, and the generated axs-017-lsm6dsm.kicad_sch.

The board is a design-stage prototype. Repository status is: schematic generated, ERC clean (0/0), netlist reviewed, PCB layout not started, not released. No board has been fabricated or assembled, so there is no first-article evidence of any kind. Every value below is a design target to verify on real hardware, not proof that an assembled module works.

1. What the board does#

The board is a 12-pin PMOD Type 2A (expanded SPI) sensor module carrying an STMicroelectronics LSM6DSM 6-axis IMU (3-axis accelerometer plus 3-axis gyroscope) in 4-wire SPI mode. VDD and VDDIO are both fed from the 3V3 PMOD rail. INT1 and INT2 are routed to PMOD pins 7 and 8 through series resistors. The auxiliary (OIS/mode 3/4) SPI interface is deliberately unused.

It contains no regulator, level shifter, or protection beyond series resistors: the host defines the supply quality and the logic levels. Nothing on the module proves the sensor is calibrated or that its data is trustworthy; that requires the register-level bring-up and self-test below.

Functional block diagram#

PMOD J1 (Type 2A, 3.3 V)                LSM6DSM U1 (LGA-14)
 1 CS_N  ──────────────┬─────────────>  pin 12 CS      (R4 10k pull-up to 3V3)
 2 MOSI  ─────────────────────────────> pin 14 SDA/SDI
 4 SCK   ─────────────────────────────> pin 13 SCL/SPC
 3 MISO  <──────R1 100R─────────────── pin 1  SDO/SA0
 7 INT1  <──────R2 100R─────────────── pin 4  INT1
 8 INT2  <──────R3 100R─────────────── pin 8  INT2
 6/12 3V3 ──┬── C1 100n ── VDD  (pin 8*)      * schematic supply pins
            └── C2 100n ── VDDIO (pin 5)
 5/11 GND ───────────────  GND  (pins 6, 7)
 Aux port: OCS_Aux (pin 10) ── 3V3; SDx (2), SCx (3), SDO_Aux (11) open

2. Safety and scope boundaries#

• This is a low-voltage 3.3 V logic module, but it has no reverse-polarity or overvoltage protection. A miswired bench supply or an incorrectly keyed PMOD cable can destroy U1 (VDD absolute range ends at 3.6 V).
• Power the module from 3.3 V only. Do not connect 5 V PMOD-lookalike hosts or 5 V logic adapters. Verify adapter IO voltage before attach.
• Do not hot-plug the PMOD connector with the host powered; PMOD has no make-first ground guarantee in typical ribbon setups.
• ESD-safe handling is required: U1 is an exposed LGA MEMS part on an unprotected connector.
• Do not drop or tap the module with hard tools to "test" the accelerometer; MEMS shock ratings are finite. Use gentle orientation flips and the built-in electrical self-test instead.
• A passing WHO_AM_I and self-test is not calibration, EMC, vibration, or environmental qualification. This guide covers first-article bring-up only.

3. Power and control sequence#

1. 3V3 is applied on J1 pins 6/12. C1 and C2 supply local decoupling for VDD and VDDIO. There is no sequencing requirement between them here because both are the same net.
2. R4 (10 kΩ to 3V3) holds CS high while the host is unconfigured. Per the datasheet, CS = 1 means "SPI idle mode / I2C communication enabled"; the pull-up guarantees the part never sees a floating CS and cannot latch a spurious SPI transaction during host FPGA configuration.
3. The LSM6DSM boots; datasheet turn-on time is 35 ms. Do not expect valid register traffic before that.
4. The first SPI access with CS driven low uses the SPI protocol; because CS idles high, I2C remains theoretically possible until the first SPI transaction. Disabling I2C afterwards (CTRL4_C, I2C_disable bit) is a recommended firmware step, not a hardware feature of this board.
5. Sensor-driven lines (SDO to MISO, INT1, INT2) each pass through 100 Ω series resistors (R1-R3), limiting current in pin-contention or hot-plug fault cases and damping reflections on ribbon cables.

Why the CS pull-up matters#

Pin 12 (CS) selects the interface: 1 = I2C enabled/SPI idle, 0 = SPI active. An unconfigured ECP5 leaves PMOD pins high-impedance; without R4, CS floats and noise can clock garbage into the part or leave it half-selected. With R4 the part sits deselected until the host deliberately drives CS low.

4. Interfaces and usage contexts#

The bench plan below covers two usage contexts; every powered test states which one it assumes:

• Context A — PMOD host FPGA: plugged into a 3.3 V PMOD port of an ULX3S-class ECP5 host. The FPGA provides 3V3/GND and drives CS/MOSI/SCK. Useful for the real streaming lesson, but the FPGA is also an unknown in first bring-up.
• Context B — standalone bench: module on a bench supply (3.3 V, current-limited to ~50 mA) with SPI driven by a lab MCU or USB-SPI adapter (e.g. FT2232H/Bus Pirate at 3.3 V). Preferred for first power-on because every signal is observable and the host is known-good.

SPI parameters (from the datasheet, Table 6): mode 0 or mode 3 (data driven on SPC falling edge, captured on rising edge; SPC idles high with CS high, which is the mode 3 description), maximum SPC clock 10 MHz. Start bring-up at 0.5-1 MHz and raise the clock only after transactions are clean. I2C fallback: the silicon supports I2C (100/400 kHz, slave address 110101x where x = SA0 = SDO pin level), but this board provides no I2C pull-ups and SDO carries R1 in series, so I2C use would need external pull-ups on PMOD pins 2 (SDA) and 4 (SCL) and is not a designed-in mode.

5. Component-by-component review#

Complete reference-designator list from generate_design.py: J1, U1, C1, C2, R1, R2, R3, R4 (plus ERC-only power flags #FLG01/#FLG02, which place no parts). All eight physical references are reviewed below.

5.1 Auxiliary-port strap review (board-specific)#

The LSM6DSM has a second (auxiliary) SPI port used in modes 3/4 for OIS or as sensor-hub wiring. This board uses mode 1 (single host SPI) and straps the aux pins as follows. Datasheet pin table (Table 2, DocID028165 Rev 7) is the reference; two straps deviate from its letter and must be consciously accepted or changed at layout review.

Review disposition: OCS_Aux = VDDIO guarantees the aux port can never be selected, which is arguably safer than floating, but both the OCS_Aux tie and the open SDx/SCx contradict the datasheet's mode-1 text. This is flagged as an open review item: either document the STEVAL evidence in the repo or move SDx/SCx to VDDIO/GND straps at layout time.

6. Datasheet summary and design interpretation#

Facts below were taken from the STMicroelectronics LSM6DSM datasheet, DocID028165 Rev 7 (official URL: <https://www.st.com/resource/en/datasheet/lsm6dsm.pdf>; product page: <https://www.st.com/en/mems-and-sensors/lsm6dsm.html>). Note on sourcing: st.com timed out repeatedly during this review, so the identical Rev 7 PDF was retrieved through the Internet Archive copy of that exact st.com URL. Re-verify against the live st.com revision before release.

7. Expected values before bench testing#

8. Manual schematic and assembly review checklist#

• Confirm U1 pin-1 orientation against the LGA-14 footprint dot before and after reflow; X-ray or angled-light inspect the perimeter pads.
• Verify VDD (pin 8) and VDDIO (pin 5) both reach 3V3 and GND pins 6/7 are both soldered — a single open GND pad may still "work" intermittently.
• Verify the section 5.1 straps as built: OCS_Aux to 3V3, SDx/SCx/SDO_Aux open, and record the deviation disposition.
• Measure R1-R4 values in-circuit before first power (R4 reads ~10 kΩ from CS_N to 3V3; R1-R3 read 100 Ω across their pads).
• Confirm C1/C2 placement is adjacent to U1 supply pins in layout review (layout does not exist yet — this is an open item, not a done item).
• Buzz all 12 J1 pins to their nets; especially confirm pins 9/10 are truly unconnected and pins 5/11 GND are common.
• Confirm no solder bridge between U1 pins 12/13/14 (CS/SPC/SDA are adjacent on the package edge).

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host identity, adapter/firmware versions, supply settings, and raw captures.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 checklist under magnification.
2. Measure 3V3-to-GND resistance in both polarities; investigate any reading under ~1 kΩ before applying power.
3. Verify CS_N-to-3V3 reads ~10 kΩ (R4) and MISO-to-U1 SDO reads ~100 Ω (R1).

B. First power, standalone (Context B)#

1. Bench supply 3.3 V, current limit 50 mA, module only — no host signals.
2. Apply power; expect quiescent current in the sub-mA range and no heating.
3. Probe CS_N (3.3 V), MISO/INT1/INT2 (defined levels, not oscillating).
4. Wait >= 35 ms (turn-on time) before any transaction.

C. First transaction bring-up: WHO_AM_I (Context B, then A)#

SPI settings: mode 0 or mode 3, 1 MHz to start, MSb first, CS active low.

Exact byte sequence (read of register 0Fh with the read bit set — the first transferred byte is RW=1 followed by address 000 1111b, i.e. 0x80 | 0x0F):

1. Assert CS low, clock the two bytes, deassert CS. Expected response: the second byte is 0x6A. Any other value: see section 10.
2. Repeat 100 times; require 100/100 identical results before proceeding.
3. Raise SCLK stepwise (2, 5, 10 MHz); require clean 0x6A at each step. 10 MHz is the datasheet maximum — do not test beyond it.
4. Optional hygiene: write CTRL4_C to set the I2C_disable bit so a noisy SCL edge can never be misread as I2C once SPI is proven.
5. Context A repeat: plug into the ECP5 PMOD port and run the same WHO_AM_I loop from fabric (or a passthrough bridge). A pass in B and fail in A isolates the problem to the host, cable, or FPGA constraints file.

D. Self-test procedure (accel and gyro)#

Per datasheet CTRL5_C (14h) and the module-specification self-test limits. Keep the module stationary and flat for the whole test.

Accelerometer (limits are full-scale independent; use FS = ±2 g):

1. Configure: CTRL1_XL (10h) = ODR 52-416 Hz, FS ±2 g. Wait for output to settle; average >= 5 samples per axis: baseline OUT_A.
2. Write CTRL5_C ST_XL[1:0] = 01 (positive-sign self-test). Wait for stable output; average >= 5 samples per axis: self-test OUT_A.
3. Compute |ST - baseline| per axis (1 LSb = 0.061 mg at ±2 g). Pass window: 90 mg <= delta <= 1700 mg on every axis.
4. Optionally repeat with ST_XL = 10 (negative sign). ST_XL = 11 is not allowed. Restore ST_XL = 00.

Gyroscope (use FS = ±2000 dps for the wide window):

1. Configure: CTRL2_G (11h) = ODR 208 Hz, FS ±2000 dps. Average >= 5 samples per axis: baseline OUT_G.
2. Write CTRL5_C ST_G[1:0] = 01 (positive sign). Average again.
3. Compute |delta| per axis (1 LSb = 70 mdps at ±2000 dps). Pass window: 150 dps <= delta <= 700 dps per axis (20-80 dps if run at ±250 dps).
4. ST_G = 10 is not allowed; 11 is negative sign. Restore ST_G = 00.

E. Data, interrupt, and FIFO checks (Context A primary)#

1. Static orientation test: place each axis up and down; expect ~±1 g on the vertical axis and ~0 g on the others (FS ±2 g).
2. Enable data-ready on INT1 (INT1_CTRL, 0Dh); scope J1 pin 7 and confirm pulses at the programmed ODR. Repeat for INT2 (INT2_CTRL, 0Eh).
3. Configure the FIFO (FIFO_CTRL1-5, 06h-0Ah) for accel+gyro at a moderate ODR; verify FIFO fill level advances and burst reads return plausible, continuous data with IF_INC = 1 multi-byte reads.
4. Sustain a burst-read loop at 10 MHz for >= 10 minutes in the ECP5 host; log CRC/consistency of samples and any WHO_AM_I re-check failures.

F. Release-only tests#

Temperature sweep, vibration/shock characterization, long-duration bias stability, EMC, and soldering-profile requalification are out of scope for this bench guide and remain open until a real layout and first article exist.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design is a deliberately minimal mode-1 SPI carrier for the LSM6DSM, and its support network (100 nF on each supply, CS pull-up, 100 Ω series resistors on all sensor-driven lines) matches the datasheet's application hints. The principal open risks are: (1) no fabricated first article exists, so nothing here is demonstrated; (2) the aux-port straps (OCS_Aux tied to VDDIO, SDx/SCx left open) deviate from the datasheet's mode-1 pin table and rest on an STEVAL-precedent argument that is not yet evidenced in this repository; (3) PCB layout — decoupling placement, SPI trace lengths for 10 MHz, and mechanical mounting stress on the MEMS — has not been started; and (4) datasheet facts were verified against an archived copy of the Rev 7 PDF because st.com was unreachable, so the live revision must be re-checked before release.