← AXS-013

Circuit review & bench-test guide

AXS-013 — APDS-9251 RGB+IR color-sensor PMOD module

Document purpose#

This document explains the axs-013-color prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, and the APDS-9251-001 manufacturer datasheet.

The board is an unfabricated, schematic-only prototype: ERC is clean (0 errors / 0 warnings) and the netlist has been reviewed, but no PCB layout exists, no board has been built, and no bench measurement has ever been taken. Every numeric value in this guide is a verification target taken from the schematic or the datasheet — it is not a measured result and is not proof that an assembled board will work.

1. What the board does#

The board is a 12-pin PMOD (Type 6 extended, I2C) module carrying a Broadcom APDS-9251-001 four-channel digital color/ambient-light sensor. Four photodiode channels (red, green, blue, and IR) integrate simultaneously into up-to-20-bit results; the green channel doubles as the human-eye-response ALS channel. A programmable threshold/variance interrupt is brought out to PMOD pin 1 as COLOR_INT. The I2C address is fixed at 0x52 (there is no address pin on this part); two solder jumpers make the on-module 4.7 kΩ bus pull-ups removable for chained-module use. Color- balance and lux math are host firmware, not on-module functions.

Functional block diagram#

PMOD J1 (2x6, Type 6 ext.)
  6/12  3V3 ────────┬─────────┬──────────┬──────────┬──────────┐
                    │         │          │          │          │
               C1 100nF   C2 1uF     R1 4.7k    R2 4.7k    R3 10k
               (HF decouple + bulk)     │ SDA_PU    │ SCL_PU    │
  5/11  GND ────────┐                  JP1 ═╗      JP2 ═╗       │
                    │                  (cut to     (cut to      │
   3/9  SCL ────────┼──────────────────────┼───── unchain)      │
   4/10 SDA ────────┼──────────────────────┘          │         │
                    v                                 │         │
             ┌──────────────┐  SCL/SDA ───────────────┘         │
             │ APDS-9251-001│                     CLR_INT ──────┤
             │      U1      │  INT (open drain) ─────┤          │
             │ fixed 0x52   │                        │ R4 100R  │
             │ R+G+B+IR ADCs│                        └──> pin 1 │
             └──────────────┘                         COLOR_INT │

2. Safety and scope boundaries#

• This is a 3.3 V logic-only module. Never apply 5 V anywhere; the APDS-9251-001 absolute maximum supply and pin voltage is 3.8 V, and its recommended VDD tops out at 3.6 V — a 3.3 V rail is in range but leaves only 0.3 V of headroom, so check the host rail is not high.
• Power from a PMOD host 3.3 V rail or a bench supply current-limited to about 50 mA. The whole module should draw well under 1 mA; more indicates a fault.
• The sensor is a 2×2 mm LGA-8 optical part. ESD precautions apply; never touch, flux-contaminate, or scratch the optical surface. Hand rework of this package is difficult — treat it as reflow-only.
• Do not hot-plug the PMOD connector during measurements.
• Decide pull-up ownership before chaining modules (section 4, JP1/JP2); stacked pull-ups may overload open-drain drivers.
• Color and lux outputs are uncalibrated raw counts. Channel ratios depend on the light source spectrum; do not treat pass/fail color numbers as colorimetry without a characterized source.
• Passing these bench tests demonstrates prototype function only, not EMC, safety, or environmental qualification.

3. Power and control sequence#

1. The PMOD host (or bench supply) applies 3.3 V to pins 6/12 and ground to pins 5/11. C1 (100 nF) provides high-frequency decoupling and C2 (1 µF) local bulk, matching the datasheet's 1 µF application circuit.
2. At power-on the device runs an internal NVM read (I2C address and trim values), then enters Standby. Until the NVM address load completes, the device NACKs all I2C traffic — allow a short delay (internal settling is typically ~5 ms once activated) before the first probe.
3. Standby is the default state: oscillator and ADCs off, I2C alive. Standby current is 1 µA typical / 2 µA maximum for U1 alone.
4. R1/R2 (through JP1/JP2) hold SDA and SCL at 3.3 V; R3 holds the open-drain INT high.
5. The host activates measurement by setting LS_EN (bit 1) in MAIN_CTRL (0x00): write 0x02 for ALS mode (IR + green channels) or 0x06 (CS_MODE + LS_EN) for RGB mode (all four channels). Active current is 130 µA typical (gain 3).
6. Conversions repeat per LS_MEAS_RATE (0x04, default 0x22 = 18-bit resolution / 100 ms conversion, 100 ms repeat) at LS_GAIN (0x05, default 0x01 = gain 3). Fresh data is flagged by MAIN_STATUS (0x07) bit 3.
7. Results sit in 3-byte, LSB-first registers 0x0A–0x15. Use block reads: during a block read in 0x07–0x18 the whole register range is locked so all bytes come from one conversion.
8. If enabled via INT_CFG (0x19), the interrupt asserts (open drain, low) when the selected channel crosses the 0x21–0x26 thresholds or varies by the 0x27 setting; R3/R4 deliver it to PMOD pin 1.

4. Interfaces#

PMOD pin map (J1, Type 6 extended)#

Pins 9/10 duplicate SCL/SDA for chaining a second I2C module.

Jumpers#

There is no address jumper: the APDS-9251-001 supports the single 7-bit address 0x52. Use bus chaining, not addressing, for multiple color modules on one host — which is exactly why JP1/JP2 exist.

Test points#

None are defined in the rev 0.1 schematic. Probe SCL/SDA/INT at the J1 pins and 3V3/GND at pins 6/5. Flag test points as a layout-review item.

5. Component-by-component review#

Every reference designator in the generated schematic is listed.

Note: APDS-9251-001 pads 1, 4, and 8 are no-connect substrate pads; the KiCad symbol hides them and nothing is wired to them by design.

6. Datasheet summary and design interpretation#

Primary reference: APDS-9251-001 datasheet (Broadcom APDS-9251-001-DS101, March 2019) — fetched directly from docs.broadcom.com; no mirror was needed. Passives: Yageo RC thick-film series, Murata GRM188 series via murata.com capacitor search.

7. Expected values before bench testing#

All values are targets to verify, not measurements.

8. Manual schematic and assembly review checklist#

• Confirm U1 orientation against the LGA-8 pin-1 marker (pad 2 = VDD, pad 3 = GND, pad 5 = SCL, pad 6 = SDA, pad 7 = INT; pads 1/4/8 NC). X-ray or careful optical inspection of the LGA joints where available.
• Verify JP1 and JP2 are bridged for standalone use; record intended state for chained builds.
• Measure R1, R2 (4.7 kΩ), R3 (10 kΩ), R4 (100 Ω) before power.
• Confirm C1 and C2 are present, correct values, and not cracked; either one shorted is a rail short.
• At layout time (still open): keep C1/C2 adjacent to U1 VDD (pad 2); keep the optical aperture over U1 free of silkscreen, mask art, and tall neighboring parts that could shade the matrix; consider test points on SDA/SCL/INT/3V3/GND.
• Confirm no solder bridges on J1, especially pins 3-4 (SCL-SDA) and 5-6 (GND-3V3).
• Confirm #FLG01/#FLG02 are schematic-only (not in BOM or placement).

9. Ordered bench-test procedure#

Assume a PMOD host (FPGA board) or a current-limited 3.3 V bench supply wired to J1 pins 6/12 (3V3) and 5/11 (GND), plus an I2C master on pins 3/4. Stop at the first abnormal result and record everything.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 checklist under magnification.
2. Measure 3V3→GND resistance in both meter polarities; investigate anything under ~10 kΩ before power.
3. Verify SDA→3V3 ≈ 4.7 kΩ, SCL→3V3 ≈ 4.7 kΩ, pin 1→3V3 ≈ 10.1 kΩ.

B. First power, no I2C traffic#

1. Set the bench supply to 3.3 V with a ~50 mA current limit; power the module.
2. Confirm supply current ≤ ~5 µA (standby) and SDA/SCL/pin 1 all idle at 3.3 V.

C. Address-ACK scan#

1. Wait ≥10 ms after power-up (NVM load), then scan all 7-bit addresses.
2. Expect an ACK only at 0x52. An early NACK at 0x52 immediately after power-up is retry-able (NVM load); a persistent NACK means U1 power, orientation, or bus wiring.

D. First-transaction bring-up (ID, status, enable)#

1. Read PART_ID: START, 0x52+W, register 0x06, repeated START, 0x52+R, read one byte — expect 0xB5 (accept 0xBx; log the revision nibble).
2. Read MAIN_STATUS (0x07) — expect the power-on bit (0x20) set on the first read and clear on the next.
3. Enable RGB mode: write register 0x00 = 0x06 (CS_MODE | LS_EN). For ALS-only bring-up write 0x02 instead.
4. Confirm supply current stepped up to the ~130 µA range.
5. Poll MAIN_STATUS until bit 3 (new data) sets — expect within ~100–200 ms at defaults.

E. Channel reads and light-response checks#

1. Block-read 12 bytes starting at register 0x0A: bytes assemble LSB-first into IR (0x0A–0x0C), green (0x0D–0x0F), blue (0x10–0x12), red (0x13–0x15); upper nibble of each third byte is zero at 18-bit.
2. Under white light (room lighting or a white LED), expect all four channels well above the ≤3-count dark floor, with green typically the largest of R/G/B.
3. Cover the sensor with an opaque cap: after the next conversion all channels should fall to ≤3 counts.
4. Channel-ratio sanity: illuminate with a red source (red LED) — red channel dominates blue; then with an IR remote — IR channel spikes while R/G/B barely move. This catches channel-order bugs in firmware (the register order IR, green, blue, red is easy to get wrong).
5. Optionally raise gain (0x05 = 0x04 for 18×) under dim light and confirm counts scale roughly ×6 from gain 3; watch for saturation at 262,143.

F. Threshold interrupt#

1. With INT_CFG (0x19) default channel (ALS/green), write an upper threshold below the current green reading (registers 0x21–0x23, LSB-first) and enable: 0x19 = 0x14 (LS_INT_SEL=01, LS_INT_EN=1).
2. Expect pin 1 (COLOR_INT) to fall below 0.4 V after the next conversion; MAIN_STATUS bit 4 sets and clears on read, releasing INT.
3. Cover the sensor and set thresholds around dark values to verify the low-threshold direction too.

G. Pull-up chain configuration (JP1/JP2)#

1. Power off. Cut JP1 and JP2; verify SDA→3V3 and SCL→3V3 now read open on this module alone.
2. Operate the module behind a pull-up-fitted module (or external 4.7 kΩ pull-ups) and repeat steps C–E — behavior must be identical.
3. Re-bridge with solder to restore standalone use; re-verify ≈4.7 kΩ.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic matches the APDS-9251-001 application circuit: 100 nF + 1 µF decoupling, recommended-value pull-ups on both bus lines and the interrupt, and a series-protected interrupt route to the host. The fixed 0x52 address makes the design simpler than its siblings (no address jumper to mis-bridge) but makes JP1/JP2 chaining the only path to multiple color modules. The principal open risks are pre-fabrication: no PCB layout yet (optical aperture, LGA-8 assembly quality, decoupling placement, and test points all unverified), no board ever powered, and firmware channel ordering (IR/G/B/R, LSB-first, block-read-only) is a likely first-bug site. The PART_ID expectation should be pinned to the upper nibble (0xB) with the revision nibble logged, since driver folklore and datasheet revisions disagree on the exact byte.