← AXS-012

Circuit review & bench-test guide

AXS-012 — APDS-9301 ambient-light PMOD module

Document purpose#

This document explains the axs-012-ambient-light prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic), the module README, and the APDS-9301 manufacturer datasheet.

The board is an unfabricated, schematic-only prototype: ERC is clean (0 errors / 0 warnings) and the netlist has been reviewed, but no PCB layout exists, no board has been built, and no bench measurement has ever been taken. Every numeric value in this guide is a verification target taken from the schematic or the datasheet — it is not a measured result and is not proof that an assembled board will work.

1. What the board does#

The board is a 12-pin PMOD (Type 6 extended, I2C) module carrying a Broadcom APDS-9301 ambient-light sensor. The sensor integrates light on two photodiode channels — CH0 (visible + IR) and CH1 (IR only) — with two 16-bit ADCs, and the host computes lux from the two raw counts using the datasheet's empirical piecewise formula. A programmable threshold interrupt (on CH0) is brought out to PMOD pin 1 as LIGHT_INT. A three-way solder jumper selects one of three I2C addresses; two solder jumpers make the on-module 4.7 kΩ bus pull-ups removable for chained-module use.

It does not regulate power (the PMOD host supplies 3.3 V), does not level-shift (3.3 V logic only), and computes nothing on-module: lux math is host firmware.

Functional block diagram#

PMOD J1 (2x6, Type 6 ext.)
  6/12  3V3 ─────────────┬──────────────┬──────────────┬───────────────┐
                         │              │              │               │
                    C1 100nF       R1 4.7k        R2 4.7k         R3 10k
                    (U1 VDD         │ SDA_PU        │ SCL_PU          │
                     decouple)     JP1 ═╗          JP2 ═╗              │
  5/11  GND ────────────┐           (cut to       (cut to             │
                        │            unchain)      unchain)           │
   3/9  SCL ────────────┼───────────────┼──────────────┘              │
   4/10 SDA ────────────┼───────────────┘              ALS_INT ───────┤
                        │                                  │          │
                        v                                  │  R4 100R │
                 ┌─────────────┐  SCL/SDA ─────────────────┤          │
   GND ── JP3:1  │  APDS-9301  │  INT (open drain) ────────┴──> pin 1 │
   3V3 ── JP3:3  │     U1      │                            LIGHT_INT │
 ADDR_SEL JP3:2 ─│ ADR_SEL     │  CH0 (vis+IR) + CH1 (IR) photodiodes │
  (1-2=0x29,     └─────────────┘  dual integrating 16-bit ADCs        │
   2-3=0x49, open=0x39)                                               │

2. Safety and scope boundaries#

• This is a 3.3 V logic-only module. Never apply 5 V to any pin; the APDS-9301 absolute maximum supply and pin voltage is 3.8 V.
• Power it from a PMOD host 3.3 V rail or a bench supply current-limited to about 50 mA at 3.3 V. The whole module should draw well under 3 mA; a higher reading indicates a fault, and a tight limit protects the sensor.
• The APDS-9301 is a small ChipLED-package optical part (MSL 3). Handle with ESD precautions and do not touch or scratch the optical surface.
• Do not hot-plug the PMOD connector while measurements are in progress; misaligned insertion can momentarily short 3V3 to signal pins.
• Do not connect this module and another pull-up-fitted module on the same chained bus without first deciding which module keeps its pull-ups (section 4, JP1/JP2). Stacked pull-ups may overload open-drain drivers.
• Sensor lux is an estimate: the datasheet states the (sensor lux)/(actual lux) ratio can range 0.65–1.35 (fluorescent) or 0.60–1.40 (incandescent). Do not treat this module as a calibrated photometer.
• Passing these bench tests demonstrates prototype function only. It is not EMC, safety, or environmental qualification.

3. Power and control sequence#

1. The PMOD host (or bench supply) applies 3.3 V to pins 6/12 and ground to pins 5/11. C1 decouples U1's VDD. There is no on-module regulator or sequencing element; U1 powers up directly.
2. On power-up the APDS-9301 is in its power-down state (CONTROL register 0h resets to 00h). Supply current should be in the power-down range (3.2 µA typical, 15 µA maximum for U1 alone).
3. R1/R2 (through JP1/JP2) hold SDA and SCL at 3.3 V. JP3's factory 1-2 bridge grounds ADR_SEL, selecting 7-bit address 0x29.
4. The host powers the device up by writing 0x03 to CONTROL (command byte 0x80, data 0x03). Active current rises to the 0.24 mA-typical / 0.6 mA-maximum range.
5. The TIMING register (1h) resets to 0x02: low gain (1×) and the 402 ms integration time. Both ADCs free-run; results transfer to the double-buffered DATA0/DATA1 registers at the end of each integration. The first read is only meaningful after one full integration period (402 ms at default settings).
6. If thresholds and the INTERRUPT register (6h) are configured, U1 pulls its open-drain INT pin low when CH0 leaves the threshold window; R3 pulls the net to 3.3 V otherwise, and R4 couples it to PMOD pin 1. The interrupt is level-style and is cleared by writing the COMMAND register with the CLEAR bit (bit 6) set.

4. Interfaces#

PMOD pin map (J1, Type 6 extended)#

Pins 9/10 duplicate SCL/SDA so a second I2C module can be chained.

Jumpers#

The three address codes come straight from the datasheet's slave-address table: GND = 0101001, float = 0111001, VDD = 1001001.

Test points#

None are defined in the rev 0.1 schematic. Until the layout adds test points, probe SCL/SDA/INT at the J1 pins and 3V3/GND at pins 6/5. Flag this as a layout-review item if hand probing proves awkward.

5. Component-by-component review#

Every reference designator in the generated schematic is listed.

6. Datasheet summary and design interpretation#

Primary reference: APDS-9301 datasheet (Avago/Broadcom AV02-2315EN). Passives: Yageo RC thick-film series, Murata GRM188R71C104KA01D (100 nF X7R) via murata.com product search.

Sensor lux formula (datasheet, high-gain 402 ms-scaled counts):

7. Expected values before bench testing#

All values are targets to verify, not measurements.

8. Manual schematic and assembly review checklist#

• Confirm U1 orientation against the ChipLED pin-1 marker (pin 1 = VDD, 2 = GND, 3 = ADR_SEL, 4 = SCL, 5 = SDA, 6 = INT). A rotated part swaps supply pins.
• Verify JP3 has exactly one bridge (1-2) as shipped, and that pads 1 and 3 cannot be bridged simultaneously by a solder blob (that is a 3V3–GND short).
• Verify JP1 and JP2 are bridged for standalone use, and record the intended state in the build sheet if this module will sit in a chain.
• Measure R1, R2 (4.7 kΩ), R3 (10 kΩ), R4 (100 Ω) values on the loose reel or in-circuit before power.
• Confirm C1 is present and not cracked; a shorted C1 is a rail short.
• At layout time (still open): keep C1 adjacent to U1 VDD; leave the optical aperture over U1 free of silkscreen and mask artwork; consider adding SDA/SCL/INT/3V3/GND test points.
• Confirm no solder bridges across the fine-pitch J1 header, especially pins 3-4 (SCL-SDA) and 5-6 (GND-3V3).
• Confirm #FLG01/#FLG02 are schematic-only (not in BOM or placement).

9. Ordered bench-test procedure#

Assume a PMOD host (FPGA board) or a current-limited 3.3 V bench supply wired to J1 pins 6/12 (3V3) and 5/11 (GND), plus any I2C master (FPGA soft core, MCU dev board, or USB-I2C adapter) on pins 3/4. Stop at the first abnormal result and record everything.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 checklist under magnification.
2. Measure 3V3→GND resistance in both meter polarities. Investigate anything under ~10 kΩ before applying power.
3. Verify SDA→3V3 ≈ 4.7 kΩ, SCL→3V3 ≈ 4.7 kΩ, pin 1→3V3 ≈ 10.1 kΩ.
4. Verify ADDR_SEL→GND ≈ 0 Ω (JP3 default) and ADDR_SEL→3V3 open.

B. First power, no I2C traffic#

1. Set the bench supply to 3.3 V with a ~50 mA current limit; power the module.
2. Confirm supply current ≤ ~20 µA (device still powered down) and that SDA, SCL, and pin 1 all idle at 3.3 V.

C. Address-ACK scan#

1. Scan all 7-bit addresses (e.g. i2cdetect-style probe or the FPGA I2C master's scan routine).
2. Expect an ACK only at 0x29. Any other ACK pattern means a JP3 or address-decode problem; no ACK means U1 power, orientation, or bus wiring.
3. (Variant check, once per design, on a sacrificial or reworked board: move JP3 to 2-3 and expect 0x49 only; cut JP3 fully open and expect 0x39 only.)

D. First-transaction bring-up (power-up and ID)#

1. Write the power-up command: START, address 0x29+W, command byte 0x80, data byte 0x03, STOP.
2. Read CONTROL back: write command 0x80, then read one byte — expect 0x03 (the datasheet's designed communication check).
3. Read the ID register: write command 0x8A, read one byte — expect 0x5x (part number nibble 0x5; record the revision nibble).
4. Confirm supply current stepped up to the ~0.3 mA active range.

E. Raw channel reads and lux math#

1. Wait at least one integration period (402 ms at the power-on default) after power-up before the first data read.
2. Read CH0 as a word: command 0xAC (0x8C + WORD bit 0x20), read two bytes, low byte first. Read CH1 with command 0xAE. (Byte-at-a-time reads with 0x8C–0x8F work but must read low before high — the low-byte read latches the high byte.)
3. Under typical office lighting (~300–500 lux), expect low-gain counts of roughly CH0 700–1200, CH1 60–150; scale ×16 and apply the section 6 formula — the result should land within a factor of ~1.4 of a reference lux meter (datasheet accuracy band).
4. Cover the sensor completely (opaque tape or a cap): after the next integration period expect CH0 ≤ 4 and CH1 ≤ 4 counts and computed lux ≈ 0.
5. Optionally write TIMING (command 0x81) = 0x12 for high gain and repeat; counts should scale ×16 (until saturation).
6. Shine an IR-heavy source (e.g. an IR remote) at the sensor: CH1/CH0 ratio should rise sharply — a good check that the two channels are not swapped in firmware.

F. Threshold interrupt#

1. Write low/high thresholds around the current CH0 value (Write Word to commands 0xA2 and 0xA4), then enable the level interrupt: command 0x86, data 0x10 (INTR=01, PERSIST=0).
2. Cover then uncover the sensor: pin 1 (LIGHT_INT) should fall to <0.4 V when CH0 leaves the window and stay low until cleared.
3. Clear by writing command 0xC0 (CMD|CLEAR); pin 1 should return to 3.3 V.

G. Pull-up chain configuration (JP1/JP2)#

1. Power off. Cut JP1 and JP2 with a scalpel; verify SDA→3V3 and SCL→3V3 now read open on this module (unpowered, module alone).
2. Connect the module behind another pull-up-fitted module (or add external 4.7 kΩ pull-ups) and repeat the address scan — behavior must be identical.
3. To restore standalone use, re-bridge JP1/JP2 with solder and re-verify ≈4.7 kΩ each.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic is a minimal, datasheet-conformant application circuit: the required 0.1 µF bypass, recommended-range pull-ups on both bus lines and the interrupt, a series resistor protecting the interrupt line, and a three-state address jumper that exactly mirrors the ADR_SEL table. The principal open risks are all pre-fabrication: there is no PCB layout yet (so no verified optical aperture, no C1 placement, and no test points), no board has ever been powered, and the lux math lives entirely in unwritten host firmware. The JP3 double-bridge failure mode (3V3–GND short through the jumper) and the sensor's wide ±35–40% lux accuracy band are the two items most worth carrying forward into the layout review and the firmware acceptance criteria.