← AXS-006

Circuit review & bench-test guide

AXS-006 — DS18B20 1-Wire temperature PMOD module

Document purpose#

This document explains the axs-006-ds18b20 PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the authoritative generator script (generate_design.py), the generated schematic, the README, the ERC report in this directory, and the DS18B20 datasheet.

This board has never been fabricated. Its status is schematic-only: ERC clean (0 errors, 0 warnings), netlist reviewed, PCB layout not started, not released. Every voltage, current, and timing number below is a design target to verify on a future first article, not a proven measurement.

1. What the board does#

The board carries one DS18B20U 1-Wire digital thermometer (catalog #6, level L2) on a single shared open-drain data line, OW, pulled to 3V3 by a 4.7 kΩ resistor. OW appears on PMOD pins 1 and 7 (same net, twice). A DNP 1×3 header, J2, extends the same bus to a second DS18B20 or a waterproof probe so the lesson grows into multi-drop ROM search. The sensor is VDD-powered (3V3 wired to its VDD pin); parasite power is not used. There is deliberately no series resistor on DQ — the line is open-drain and the pull-up already limits fault current; a series element would only degrade the shared bus edges.

The host must drive OW only as open-drain: output 0 or release to input, never drive 1. All protocol timing — reset, presence, and 60 µs bit slots — is generated by the FPGA fabric; that is the exercise.

Functional block diagram#

   3V3 (PMOD 6/12) ──┬───────────────┬──────────────┐
                     │               │              │
                    R1 4.7k         C1 100n        (J2.1, DNP)
                     │               │              │
   OW (PMOD 1, 7) ───┴──── DQ ── U1 DS18B20U ── VDD─┘
                     │            │
                     ├───────── (J2.2, DNP: external probe DQ)
                     │
   GND (PMOD 5/11) ──┴──── U1 GND ── C1 ── (J2.3, DNP)

2. Safety and scope boundaries#

• 3.3 V logic only. The DS18B20 tolerates up to 5.5 V, but the PMOD host does not necessarily; never mix a 5 V bus master onto this module's OW net.
• Absolute maximum on any DS18B20 pin is −0.5 V to +6.0 V. Long external probe leads on J2 act as antennas — keep probe cables short on the bench and add transient thinking before any field/waterproof-probe deployment; the module has no ESD or surge parts on OW by design.
• The host FPGA pin on OW must be open-drain (drive 0 / release). Driving a hard 1 while U1 or a J2 device transmits a 0 fights a ~100 Ω internal sink transistor with no series limit — this is the module's one real electrical-abuse path.
• In standalone testing use a current-limited bench supply (3.3 V, limit 50 mA or less).
• Do not hold OW low more than 480 µs unintentionally: every device on the bus resets (this is also a useful deliberate recovery action).
• Parasite-power experiments (VDD grounded, strong pull-up) are not supported by this schematic as built — U1 VDD is hard-wired to 3V3.
• Passing these bench tests is not EMC, ESD, safety, or environmental qualification, and the sensor's ±0.5 °C accuracy claim is untested until compared against a reference thermometer.

3. Power and signal sequence#

1. 3V3 and GND arrive on PMOD pins 6/12 and 5/11 (or the bench supply). C1 decouples U1's VDD locally. R1 pulls OW to 3V3: the idle bus state is high and must be, or nothing works.
2. At power-up U1 auto-recalls its EEPROM (TH, TL, config) to the scratchpad and loads the temperature register with the power-on default +85 °C (0x0550) — reading 85.0 °C means "no conversion performed yet," a diagnostic sign, not a fault.
3. The master begins every transaction with a reset pulse: OW driven low for ≥ 480 µs, then released. R1 pulls the line high; U1 waits 15–60 µs, then answers with a presence pulse (low for 60–240 µs).
4. The master sends one ROM command (first bring-up read: 0x33 Read ROM, single device only), then a function command (e.g. 0x44 Convert T, then reset + ROM + 0xBE Read Scratchpad).
5. Bits move in master-initiated 60–120 µs time slots, LSB first. During conversion (≤ 750 ms at 12-bit) the master may poll read slots: 0 = busy, 1 = done — possible only because VDD is wired (a parasite-powered part would need the line held high instead).

Why VDD-powered and not parasite#

With VDD wired, conversions draw their up-to-1.5 mA operating current from 3V3, so the bus stays available for done-polling and other traffic, multiple sensors can convert simultaneously, and no strong (MOSFET) pull-up is needed. Parasite mode would require VDD grounded and the master to clamp DQ high within 10 µs of issuing 0x44/0x48 for the full conversion/copy time; the datasheet also discourages parasite power above 100 °C. The 0xB4 Read Power Supply command must return 1 on this board — a 0 indicates U1's VDD pin is not actually powered (open joint), the classic hidden assembly fault.

4. Interfaces#

OW on both pin 1 and pin 7 lets either standard PMOD GPIO position own the bus; connect the master to one and probe on the other.

No test points exist in the current schematic; probe the PMOD pins, R1 pads, and U1 pads directly.

5. Component-by-component review#

(#FLG01/#FLG02 are ERC power flags, not physical parts.)

6. Datasheet summary and design interpretation#

Primary reference: DS18B20 datasheet (Analog Devices) (mirror used for this review); DS18B20 product page. Pull-up: Yageo RC series. Check the latest revision before procurement.

7. Expected values before bench testing#

All values are calculated/datasheet targets — no board has ever been built or measured.

DC values:

1-Wire timing capture expectations (scope, 2–5 V/div is not needed — 1 V/div, 100 µs/div for reset, 10 µs/div for slots; trigger falling edge):

Protocol bring-up expectations:

8. Manual schematic and assembly review checklist#

• Verify J1 pin 1 location and orientation against the PMOD spec; buzz all 12 pins pad-to-socket. Confirm OW really lands on PMOD pins 1 and 7.
• Confirm U1 (µSOP-8) orientation dot against the footprint. Per the datasheet pinout for the 8-pin package: GND pin 5, DQ pin 4, VDD pin 3, others NC. A rotation is an abs-max event — check before power.
• Confirm U1 VDD pad is soldered (the "hidden parasite" fault): after assembly, buzz U1 VDD pin directly to PMOD pin 6.
• Measure R1 = 4.7 kΩ from OW to 3V3; confirm nobody substituted a series resistor into DQ (design rule: there must be none).
• Confirm C1 sits close to U1's VDD/GND in the eventual layout (layout not started; carry this to layout review) and is not shorted.
• Confirm J2 is DNP for the core build; if populated for a lesson, verify the 3V3/OW/GND order printed on the silk against the schematic before attaching any probe.
• Confirm no pull-up was added at the host side too (two parallel pull-ups lower the effective resistance and raise VOL stress on small sinks — one 4.7 kΩ on the module is the design).

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, equipment, and operator. Phases A–D are standalone (bench supply + any 1-Wire-capable master or the FPGA dev board wired manually); phase E is the PMOD host context; phase F is multi-drop.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 checklist under magnification.
2. Ohmmeter: 3V3-to-GND open; OW-to-3V3 ≈ 4.7 kΩ; OW-to-GND high (not ~100 Ω or 0 — that suggests a DQ bridge or damaged U1).
3. Buzz U1 pin 3 (VDD) to PMOD pin 6 and U1 pin 5 (GND) to PMOD pin 5.

B. Standalone power-up (current-limited bench supply)#

1. Bench supply 3.30 V, current limit ≤ 50 mA, + to PMOD 6/12, − to 5/11.
2. Power on: supply current ≈ µA-scale (below most supplies' resolution). mA-scale idle current means a short (C1, U1) — power down.
3. DMM OW: 3.30 V idle on both pin 1 and pin 7.
4. Briefly short OW to GND through the meter/probe and release: line returns crisply to 3.30 V (pull-up alive).

C. Standalone reset/presence capture (the go/no-go test)#

1. Keep the bench supply. Connect a 1-Wire master to OW/GND (FPGA pin configured open-drain, a USB 1-Wire adapter, or an MCU running a known 1-Wire library — any master works; the module doesn't care).
2. Scope OW at 100 µs/div, single-shot on falling edge. Issue a reset.
3. Verify against section 7: master low ≥ 480 µs; after release, a sensor-driven presence low beginning 15–60 µs later and lasting 60–240 µs. This single capture proves power, pull-up, U1 life, and DQ connectivity simultaneously.
4. No presence: see section 10 before touching anything else.

D. Standalone protocol bring-up#

1. Issue reset + 0x33 Read ROM. Verify family code 0x28 and the ROM CRC. Record the full 64-bit ROM (it identifies this exact unit forever).
2. Issue reset + 0xCC + 0xBE. Verify the +85 °C power-up default (0x50, 0x05), config 0x7F, and scratchpad CRC.
3. Issue reset + 0xCC + 0xB4 + one read slot. Expect 1 (VDD powered).
4. Issue reset + 0xCC + 0x44. Poll read slots: 0 (busy) then 1 (done); time it — ≤ 750 ms. Watch the supply current blip (~1 mA).
5. Reset + 0xCC + 0xBE: read all 9 bytes, verify CRC-8, convert (raw/16 °C) and sanity-check against a reference thermometer (±0.5 °C class).
6. Capture write-0, write-1, and read slots on the scope and check each against the section 7 slot table — especially that your master samples reads inside 15 µs.
7. Optional: 0x4E write TH/TL/config to 9-bit (config 0x1F), re-convert, confirm ≤ 93.75 ms and 0.5 °C granularity; power-cycle to confirm the volatile scratchpad reloads from EEPROM (or 0x48 Copy to persist).
8. Hold OW low > 480 µs mid-transaction on purpose: everything resets and the next reset/presence works — confirms the documented bus-recovery behavior.

E. PMOD host context (host provides 3.3 V)#

1. Confirm in the host constraints that the OW pin is open-drain or emulated as such (drive 0 / high-Z), with the host's internal pull-up disabled, before loading the bitstream.
2. Plug into the host PMOD socket. Repeat phase C's reset/presence capture probing OW on whichever PMOD pin (1 or 7) the master is not using.
3. Run the fabric 1-Wire master through the phase D sequence (ROM read, 85 °C default, 0xB4, convert, scratchpad + CRC).
4. Re-measure OW rise time in-system: host socket, cable, and FPGA pin add capacitance; edges must still satisfy the 15 µs read budget.

F. Multi-drop extension (J2 populated)#

1. Power down, populate/verify J2, attach the second DS18B20 or probe with the pin order triple-checked (3V3 / OW / GND).
2. Repeat reset/presence: presence pulses now overlap (wired-AND) and may look longer; that is normal.
3. Confirm 0x33 now returns corrupted/ANDed data (expected — this is the lesson), then run 0xF0 Search ROM to enumerate both ROMs, and 0x55 Match ROM to read each sensor individually with CRC checks.
4. Re-measure rise time with the probe cable attached; if read slots start failing CRC, edge speed versus the 15 µs read window is the first suspect (a stronger pull-up, e.g. 2.2 kΩ, is the classic mitigation but is a design change — record it, don't bodge it silently).

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The circuit is the canonical VDD-powered single-sensor 1-Wire node — sensor, one 4.7 kΩ pull-up matching the datasheet's ≈5 kΩ recommendation, one decoupler — and its deliberate omissions (no series resistor on DQ, no ESD parts, no host-side pull-up) are consistent with an open-drain shared bus and are documented rather than accidental. The design decisions that most deserve bench confirmation are the ones software can silently mask: that U1's VDD pin is genuinely soldered and powered (0xB4 must return 1), that the master's read sampling lands inside the 15 µs valid window at real in-system bus capacitance, and that rise time survives the J2 probe-cable extension. The +85 °C power-on default and the CRC-8 on every ROM and scratchpad read are built-in diagnostics — use them, don't skip them. The principal open risk is simply that no board has ever been fabricated: every number in this guide is a datasheet or calculated target awaiting a first article, and PCB layout (decoupler placement, OW routing to both PMOD pins) has not even started.