← AXS-002

Circuit review & bench-test guide

AXS-002 — Hall-effect + reed switch PMOD module

Document purpose#

This document explains the axs-002-hall-reed PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the implemented schematic generator (generate_design.py), the module README, the sensor-line conventions in ../README.md, and the verified Pmod-spec notes in ../../pmod-common/PMOD-SPEC-NOTES.md.

This board is a schematic-complete prototype. It has NOT been laid out, fabricated, assembled, or bench-verified. Repository status: schematic generated, ERC clean (0 errors / 0 warnings), netlist reviewed; PCB layout not started. Every voltage, current, distance, and timing figure below is a design target to verify on a first article, not proof that a board works.

1. What the board does#

Two magnetic detectors sit side by side on one 3.3 V PMOD Type 1 (GPIO) module: a Diodes AH1806 solid-state omnipolar hall-effect switch and a Coto CT10 mechanical reed switch. The same hand-held magnet exercises both. Each detector pulls its line low while a magnet is present; both lines idle high through 10 kΩ pull-ups. The teaching point is the contrast: the hall switch gives a bounce-free (but sampled) edge, while the reed contact bounces and motivates the FPGA debounce exercise.

The module has no other function: no ADC, no configuration, no interrupts beyond the two level-type lines themselves.

Functional block diagram#

                     3V3 (PMOD pins 6/12)
                      │
        ┌─────────────┼───────────────┬────────────┐
        │             │               │            │
       R1 10k        C1 100nF        R3 10k        │
        │             │ (U1 bypass)   │            │
        │            GND              │            │
        v                             v
   HALL_OUT ── R2 100R ── HALL     REED_SENSE ── R4 100R ── REED
        ^  (PMOD pin 1)               ^        (PMOD pin 2)
        │ open-drain                  │ contact to GND
   U1 AH1806-W                    SW1 CT10 reed switch
   omnipolar hall switch              │
        │                            GND
       GND

   Magnet present  → HALL low (clean, sampled ~every 75 ms)
   Magnet present  → REED low (immediate, but bouncy)

2. Safety and scope boundaries#

• This is a 3.3 V logic module; there are no hazardous voltages. The main risks are to the hardware, not the operator.
• Power it only from a Digilent-compatible 3.3 V PMOD host (AruviX ECP5 rev-A or equivalent) or a bench 3.3 V supply with the current limit set low (10–20 mA is ample; the whole module draws well under 1 mA).
• Do not exceed 3.6 V. The AS-FETCHED AH1806 datasheet revision (DS36104 Rev 2-2) specifies a 2.5–3.6 V operating range with a 5 V transient-only absolute maximum. The schematic description claims "2.5-5.5 V", which matches newer datasheet revisions' marketing text but was NOT verified here — treat 3.6 V as the ceiling until the current revision is checked.
• The reed switch capsule inside the CT10 molding is glass. Do not flex the board near SW1, drop the module, or exceed the 10 G vibration / 100 G shock ratings; a cracked capsule can fail open or closed permanently.
• Never switch an inductive or mains load through SW1's line — the reed contact rating (10 W, 500 mA max switched) is irrelevant here because the contact only pulls a 10 kΩ pull-up, and nothing else may be wired to it.
• Strong test magnets (neodymium) damage magnetic media, mechanical watches, and pacemakers, and can slam together and shatter. Handle deliberately.
• Do not hot-plug the PMOD connector at odd angles; a shifted plug can short 3V3 to a driven line. Align pin 1 before applying power.
• A working bench result is not EMC, ESD, or environmental qualification.

3. Theory of operation and signal sequence#

1. At power-up, C1 stabilizes U1's supply. Per the fetched datasheet, U1's output state is valid after its second internal operating cycle, typically ~150 ms after power-on; ignore both lines for the first 250 ms.
2. With no magnet, U1's open-drain output is off and SW1 is open, so R1 and R3 hold HALL_OUT and REED_SENSE at 3.3 V. HALL and REED read high at the host through the 100 Ω series resistors R2/R4.
3. U1 is a micropower duty-cycled part: it wakes for ~75 µs every ~75 ms (max 125 ms), samples the field, and latches the result. When the magnitude of the flux through the package exceeds the operate point (Bop, either pole — omnipolar), the output MOSFET turns on and HALL_OUT is pulled low. It releases only when the field falls below the release point (Brp): built-in magnetic hysteresis, so the edge cannot chatter.
4. SW1's ferromagnetic reeds close directly under the applied field — response is immediate (sub-millisecond) but the contact physically bounces on closure, producing a burst of edges before settling low.
5. Consequence for the lesson: the hall line changes state cleanly but only at sample instants (a magnet transit faster than one ~75–125 ms period can be missed entirely); the reed line responds instantly but dirtily.

4. Interfaces#

PMOD Type 1 (GPIO) per Digilent Pmod Interface Specification 1.2.0. Pin 1 is the rightmost pin of the upper row viewed from the module top with the connector toward you (verified in ../../pmod-common/PMOD-SPEC-NOTES.md).

Both signals are module-driven inputs to the host, active low, idle high. On an AruviX ECP5 rev-A standard socket they additionally pass the host's 200 Ω series resistors and ESD diodes (per the adopted Pmod spec practice).

There are no dedicated test points in the schematic. Useful probe nodes: HALL_OUT (R1/R2 junction, before the series resistor), REED_SENSE (R3/R4 junction), 3V3 and GND at C1's pads.

5. Component-by-component review#

5.1 Detectors and connector#

5.2 Pull-ups, series protection, decoupling#

6. Datasheet summary and design interpretation#

7. Expected values before bench testing#

All values are design targets on an unbuilt board.

8. Manual schematic and assembly review checklist#

• Confirm J1 pin-1 orientation against the Pmod-spec recipe (rotation, square pad top-right) before layout sign-off; a mirrored plug puts 3V3 on a signal pin.
• Verify U1 orientation: SC59 pin 1 = VDD, 2 = GND, 3 = OUTPUT. A rotated part reverse-powers the die.
• Confirm the branded-face/marking side of U1 versus the intended magnet approach direction: Bops is defined for a south pole facing the part MARKING side. Document which board face the user should present the magnet to.
• Resolve the CT10 part-number/sensitivity discrepancy (schematic says 10–15 AT, MPN decodes as 15–40 AT) and confirm G4 orderability.
• Check the reflow profile against the CT10-G4 limit (226 °C max on the leads, 1 min) — stricter than a standard lead-free profile peak.
• Confirm C1 is placed within a few mm of U1 VDD in layout.
• Measure R1–R4 values in-circuit before first power (10 k / 100 / 10 k / 100 Ω).
• Verify the schematic's AH1806 supply-range note (2.5–5.5 V) against the latest diodes.com datasheet revision; the fetched Rev 2-2 says 2.5–3.6 V.
• Confirm silkscreen carries module name, Type 1 badge, pin-1 marker.

9. Ordered bench-test procedure#

Test context: either an AruviX ECP5 rev-A / Digilent-compatible 3.3 V PMOD socket (host FPGA pins configured as inputs, or simply unconfigured), or a bench 3.3 V current-limited supply (≤20 mA limit) on pins 6/12 (3V3) and 5/11 (GND) with a DMM, an oscilloscope, and optionally a logic analyzer. You also need: one small neodymium or alnico test magnet (pole faces identifiable), a non-magnetic ruler or caliper jig, and non-magnetic tweezers. Stop at the first abnormal result. Record board serial, magnet identity, equipment, ambient, and operator with every capture.

A. Unpowered inspection and resistance tests#

1. Visual inspection under magnification: U1 orientation, SW1 body intact (no molding cracks), R1–R4/C1 values and fillets, J1 pin-1 marking.
2. With no magnet near the board, measure resistance: 3V3-to-GND (expect high, ≥100 kΩ class), HALL-to-3V3 (≈10.1 kΩ via R2+R1), REED-to-3V3 (≈10.1 kΩ via R4+R3), REED-to-GND (open).
3. Hold the magnet on SW1 and re-measure REED-to-GND: ≈100 Ω (R4 plus ≤0.15 Ω contact). Confirms the reed closes before any power is applied.

B. First power-up, static levels#

1. Apply 3.3 V with the current limit set. Confirm supply current is in the tens-of-µA range at idle. Investigate anything above ~1 mA.
2. After ≥250 ms, confirm HALL and REED both read ~3.3 V.
3. Bring the magnet to U1: HALL drops low (≤0.3 V at HALL_OUT). Remove it: HALL returns high. Repeat on SW1 for REED.
4. If on a PMOD host, run a trivial FPGA design that mirrors pins 1/2 onto LEDs and confirm both channels end-to-end.

C. Magnet approach/release hysteresis test (both detectors)#

This is the core characterization. Fix the board flat; slide the magnet toward each sensor along a ruler at a constant height and orientation.

1. Hall operate/release distance. Approach U1 slowly (well under 1 cm/s, so the ~75–125 ms sampling adds <1 mm of error). Record the distance at which HALL asserts (operate). Withdraw slowly; record where it releases. Because Brp (20 G typ) < Bop (30 G typ), the release distance must be larger than the operate distance — that gap is the built-in hysteresis. Repeat 5 times; distances should repeat tightly (solid-state, no wear).
2. Omnipolar check. Flip the magnet to present the opposite pole and repeat step 1. Both poles must trip the output (Bops/Bopn are symmetric ±15–45 G bands). Operate distances for the two poles will be similar but not identical — the min/typ/max bands are wide; record both.
3. Reed operate/release distance. Repeat the slow approach along SW1's long axis (reeds respond to axial field). Record operate and release distances; release distance should again exceed operate distance (release AT band is lower than pull-in). Note the reed is NOT omnipolar in the hall sense — either pole closes it, but sensitivity depends strongly on magnet orientation relative to the reed axis; record the orientation used.
4. Compare: expect the hall's trip distances to repeat more cleanly than the reed's (mechanical parts show more spread), and expect BOTH devices to show operate < release distance.
5. Fast-transit contrast (optional but instructive). Sweep the magnet past both sensors quickly (<50 ms transit). The reed will emit a pulse burst; the hall may miss the event entirely if the transit falls between ~75–125 ms samples. Capture both lines simultaneously.

D. Bounce capture and edge-quality contrast#

1. Scope REED_SENSE (or REED), single-shot, falling-edge trigger, 1 ms/div then zoom. Snap the magnet onto SW1. Capture the closure: expect a burst of make/break edges settling low. Measure total bounce duration over 10 closures; the ~0.1–1 ms class expectation is UNVERIFIED (the CT10 datasheet publishes no operate/release times) — whatever you measure is the number the HDL debouncer must beat. Also capture release (opening); reed opening typically bounces less — verify.
2. Scope HALL the same way. Expect exactly one clean falling edge per assert event (fall time limited by R1×line capacitance, order of µs on a bench setup), with NO bounce, but with up to ~125 ms latency from the field crossing. This side-by-side pair of captures is the module's teaching artifact — save both.
3. With a logic analyzer at ≥1 MHz sample rate, count bounce edges per closure across 20 closures for the debounce-exercise dataset.

E. Supply-margin and idle-current sweep (bench supply only)#

1. Sweep 3V3 from 3.0 to 3.6 V; confirm both channels still operate and idle current stays in range. Do NOT sweep above 3.6 V (fetched-revision operating limit).
2. At 3.3 V, log idle current for 10 minutes; a slow upward drift may indicate a stressed U1 or contaminated flux residue leaking across R1/R3.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The circuit is minimal and coherent: two independent active-low channels, each with the line rules the sensor family mandates (10 kΩ pull-up, 100 Ω series element, local decoupling), on a correctly-typed PMOD Type 1 pin map. The AH1806's open-drain output, recommended pull-up range, and bypass capacitor usage all match the fetched datasheet. The principal open items before release are: (1) the CT10 sensitivity discrepancy — the MPN CT10-1540-G4 decodes as a 15–40 AT band while the schematic claims 10–15 AT, and the G4 lead form's published operate range ends at 30 AT, so the exact orderable part must be re-selected or the description corrected; (2) the AH1806 supply-range note (2.5–5.5 V) disagrees with the fetched Rev 2-2 datasheet (2.5–3.6 V) and must be checked against the current revision; (3) reed bounce timing is unpublished and must be measured, not assumed; and (4) everything here remains a paper design — no layout, fabrication, or first-article evidence exists yet.