← AXS-001

Circuit review & bench-test guide

AXS-001 — Button & switch pack PMOD module

Document purpose#

This document explains the axs-001-buttons PMOD module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the authoritative generator script (generate_design.py), the generated schematic, the README, and the ERC report in this directory.

This board has never been fabricated. Its status is schematic-only: ERC clean (0 errors, 0 warnings), netlist reviewed, PCB layout not started, not released. Every voltage, current, and timing number below is a design target to verify on a future first article, not a proven measurement.

1. What the board does#

The board is a passive input pack for the AruviX sensor line (catalog #1, level L1, GPIO). Four tactile buttons drive PMOD pins 1–4 active low (10 kΩ pull-up to 3V3, button shorts the node to GND), and one SPDT slide switch drives PMOD pin 7 with a rail level (3V3 or GND) selected by its position. There is deliberately no hardware debouncing: observing and debouncing contact bounce in FPGA fabric is the point of the module. Every module-driven line leaves through a 100 Ω series resistor (the line-wide miswire-tolerance rule).

There are no active devices, no regulators, and no protection diodes. The module consumes essentially zero current until a button is held.

Functional block diagram#

        3V3 (PMOD 6/12)
         │
         ├── R1 10k ──┬── BTN1_N ── R5 100R ──> BTN1 (PMOD 1)
         │           SW1 (to GND)
         ├── R2 10k ──┬── BTN2_N ── R6 100R ──> BTN2 (PMOD 2)
         │           SW2 (to GND)
         ├── R3 10k ──┬── BTN3_N ── R7 100R ──> BTN3 (PMOD 3)
         │           SW3 (to GND)
         ├── R4 10k ──┬── BTN4_N ── R8 100R ──> BTN4 (PMOD 4)
         │           SW4 (to GND)
         │
         └──(throw A)─┐
                     SW5 SPDT ── SLIDE_C ── R9 100R ──> SLIDE (PMOD 7)
        GND ─(throw B)─┘

        GND (PMOD 5/11)

2. Safety and scope boundaries#

• The module is 3.3 V logic only. Never connect it to a 5 V PMOD-shaped host or a 5 V bench supply; nothing on the board limits rail voltage.
• In standalone testing, use a current-limited bench supply (3.3 V, limit 50 mA or less). A wiring mistake into VCC/GND pins is otherwise unlimited.
• The host FPGA pins connected to BTN1–BTN4 and SLIDE must be configured as inputs. If a host output fights a pressed button or the slide switch, only the 100 Ω series resistor (about 33 mA at 3.3 V) limits the contention current. That resistor is a miswire mitigation, not an invitation.
• SW5 is assumed non-shorting (break-before-make). Do not treat the brief mid-travel float on SLIDE as a valid logic level.
• This is a prototype for learning. Passing these bench tests is not EMC, ESD, safety, or environmental qualification.

3. Signal and power sequence#

1. 3V3 and GND arrive on PMOD pins 6/12 and 5/11 (or the bench supply). There is no local regulation or bulk capacitance; the host rail is used directly.
2. With no button pressed, R1–R4 pull BTN1_N–BTN4_N to 3V3. The PMOD lines BTN1–BTN4 read logic 1 through R5–R8 (no DC load, so no drop).
3. Pressing SWx shorts BTNx_N to GND. The line falls to about 0 V; the only static current is 3.3 V / 10 kΩ ≈ 0.33 mA through the pull-up.
4. On press and release the mechanical contacts bounce for a device- and press-dependent time (typically a few ms; Alps does not publish a bounce spec for this part). The host sees multiple edges — this is expected and is the debouncing lesson.
5. SW5's common (SLIDE_C) is tied to 3V3 in one position and GND in the other, so SLIDE always carries a defined level except during the brief non-shorting transition, when the line floats (no pull resistor on SLIDE_C — position, not level, defines the state).

4. Interfaces#

One connector only. PMOD Type 1 (GPIO), Digilent spec 1.2, 2×6 right-angle male plug.

Buttons read 0 when pressed. SLIDE reads the switch position. Pins 8–10 are unconnected. There are no test points in the current schematic; probe the PMOD pins and the resistor pads directly.

5. Component-by-component review#

5.1 Connector#

5.2 Buttons and slide switch#

5.3 Resistors#

(#FLG01/#FLG02 in the schematic are ERC power flags, not physical parts.)

6. Datasheet summary and design interpretation#

Official references: Alps SKQGABE010 product page, C&K JS-series datasheet (C&K is now Littelfuse; the URL redirects to the current hosting), Yageo RC thick-film series. Check the latest revision before procurement.

7. Expected values before bench testing#

All values are calculated targets — no board has ever been built or measured.

8. Manual schematic and assembly review checklist#

• Verify J1 pin 1 location and that the plug orientation matches the PMOD spec (pin 1 top-left when mated); buzz all 12 pins from pad to host socket.
• Confirm 3V3 is not shorted to GND with SW5 in both positions before first power (a throw-side bridge only shows in one position).
• Confirm the tactile footprint pin pairing: SKQG parts have two pins per side internally connected — a wrong library pairing makes the switch a permanent short or a permanent open. Buzz each SWx pad pair pressed and released.
• Measure R1–R4 = 10 kΩ and R5–R9 = 100 Ω in circuit (values are distinct enough to catch a reel swap).
• Confirm no pull resistor was "helpfully" added to SLIDE_C and no debounce capacitor was added anywhere — both would defeat the module's purpose.
• Inspect SW5 throws for solder bridging (rail-to-rail risk) and SW1–SW4 for skewed placement that could jam the actuator.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, equipment, and operator. Phases A–C are standalone (bench supply); phase D repeats the functional checks on a real PMOD host.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 checklist under magnification.
2. Ohmmeter 3V3-to-GND: expect open. Repeat with SW5 in the other position.
3. For each button channel: PMOD pin to 3V3 ≈ 10.1 kΩ released; PMOD pin to GND ≈ 100 Ω held. Verify pin N responds to switch N only (no crosstalk from solder bridges between adjacent channels).
4. PMOD pin 7 to 3V3 ≈ 100 Ω in one SW5 position, pin 7 to GND ≈ 100 Ω in the other, never both.

B. Standalone power-up (current-limited bench supply)#

1. Set a bench supply to 3.30 V with the current limit at 50 mA. Connect + to PMOD pins 6/12 and − to pins 5/11 (use both pin pairs if the harness allows; they are commoned on the module).
2. Power on with nothing pressed: supply current should read ≈ 0 mA (below the resolution of most bench supplies). Any mA-scale idle current means a short or wrong resistor — power down and investigate.
3. DMM each line: BTN1–BTN4 = 3.30 V, SLIDE = rail level matching position.
4. Press each button in turn: its line falls to < 5 mV and supply current steps up by ≈ 0.33 mA. Hold all four: ≈ 1.32 mA total. Release: levels and current return.
5. Toggle SW5 both ways several times; pin 7 alternates cleanly between 3.30 V and < 5 mV.

C. Standalone dynamic tests (scope)#

1. Scope on a BTNx PMOD pin, 1 V/div, single-shot trigger on falling edge, 1 ms/div. Press the button: capture the press bounce burst. Measure the time from first falling edge to the last transition — this is the number your fabric debouncer must exceed. Repeat on the rising (release) edge, which often bounces differently.
2. Repeat for all four buttons and several press speeds/angles; record the worst-case bounce duration per switch. Expect unit-to-unit and press-to-press variation; Alps specifies no maximum.
3. Scope SLIDE during slow actuation: expect a defined level, a brief noisy /floating interval (non-shorting transition), then the opposite level. Confirm no simultaneous-rails behavior (that would be a shorting or bridged switch).
4. Optional miswire-rule check (bench supply still current-limited): with a button held, source 3.3 V through an ammeter into that BTN pin. Expect ≈ 33 mA limited by the 100 Ω series resistor. Keep it brief — this dissipates ~0.11 W in an 0.1 W part.

D. PMOD host context (host provides 3.3 V)#

1. Plug into the FPGA host PMOD socket. Confirm host pins for BTN1–BTN4 and SLIDE are constrained as inputs (with host pull-ups disabled, so the module's 10 k pull-ups are the only ones — a host pull-down would form a divider) before configuring the bitstream.
2. Repeat the section B functional sweep reading levels at the host socket pins (or via a simple fabric design that mirrors inputs to LEDs).
3. Run the raw-input demo: confirm each button and the slide maps to the expected PMOD pin per the section 4 table.
4. Run the edge-detection exercise without a debouncer and count events per press — multiple counts per press confirm bounce reaches the fabric. Then enable the debouncer sized from the phase C measurement and confirm exactly one event per press and one per release.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design is intentionally minimal and internally consistent: active-low buttons with defined idle levels, a rail-tied slide switch so SLIDE is never statically floating, and a uniform 100 Ω series-resistor rule that bounds host-miswire current at ~33 mA. Deliberate omissions — no debounce network, no pull on SLIDE_C, no rail protection — are documented lessons, not oversights, but they define the board's limits: it must only ever meet a 3.3 V input-configured host. The principal open risks are that nothing has ever been fabricated or measured, that switch footprint pin-pairing errors are the most likely silent build fault, and that a solder bridge across SW5's throws is the only single defect that directly shorts the host rail. Bounce duration is unspecified by the switch vendor and must be characterized per unit on the bench before the fabric debouncer constant is declared adequate.