Circuit review & bench-test guide

AXO-016 — PS/2 keyboard/mouse PMOD module

Design-stage — board not yet fabricated

Document purpose#

Component-level explanation and bench-test plan for axo-016-ps2, from generate_design.py, the module README.md, and the BSS138 + PS/2 interface references. Never fabricated; values are verification targets. A keystone for the standalone-computer path (PS/2 keyboard in for AruviOS).

1. What the board does#

Adapts a 5 V open-collector PS/2 device (keyboard/mouse) to the 3.3 V PMOD. Because no stock Mini-DIN-6 footprint exists, the connector is a 1×4 pigtail socket (VCC/GND/CLK/DATA) — the device attaches via a Mini-DIN-6 pigtail. CLK and DATA are bidirectional open-collector; each is level-shifted with the classic BSS138 + dual-10 k circuit.

EXT 5V J3 ─> J2 pigtail VCC (keyboard power) ; GND common
J2 CLK/DATA (5V O.C.) ─> BSS138 shifters (10k each side) ─> PMOD 1 CLK / 2 DATA (3.3V)

2. Safety and scope boundaries#

Two rails: PMOD 3.3 V (logic side) and external 5 V (J3, keyboard power). Most PS/2 keyboards need 5 V at ~50–100 mA; some tolerate 3.3 V (document per device). Bring up 3.3 V first, then 5 V.
Standalone: 3.3 V into 3V3/GND and 5 V into J3, current-limited (~200 mA).
The 5 V rail powers the keyboard only; the BSS138 circuit ensures the PMOD side never exceeds 3.3 V.
Unreleased prototype.

4. Interfaces#

J1 PMOD Type 1: 1 PS2_CLK, 2 PS2_DATA, 5/11 GND, 6/12 3V3.
J2 1×4 pigtail socket: VCC / GND / CLK / DATA (verify pigtail order, Section 4a).
J3 external 5 V + GND.

4a. PLUG-IN / PIGTAIL VERIFICATION#

Mini-DIN-6 (PS/2) pinout is standardized (1 DATA, 3 GND, 4 VCC, 5 CLK) but pigtail wire colors vary. Before power: buzz the pigtail to identify VCC, GND, CLK, DATA and match them to J2's silkscreen. A VCC/GND swap can damage the keyboard; a CLK/DATA swap just fails to communicate.

5. Component-by-component review#

J2 (1×4 pigtail socket): device interface. If VCC/GND swapped: keyboard damage — hence Section 4a.
2× BSS138 (SOT-23 N-FET level shifters), one per bidirectional line: the classic circuit — FET source on the 3.3 V side, drain on the 5 V side, gate to 3.3 V, 10 kΩ pull-up on each side. It passes open-collector lows in both directions and clamps the 3.3 V side high to 3.3 V. If a BSS138 is absent: the 5 V open-collector high (pulled to 5 V) reaches the PMOD directly — over- voltage on the FPGA pin. If a pull-up is missing: that side can't idle high, so the bus can't signal.
4× 10 kΩ (two per line): the pull-ups that make the open-collector bus work and set the shifter idle levels. If too large: slow edges corrupt the ~10–16 kHz PS/2 clocking; if absent: dead line.
Decoupling 100 nF (5 V and 3.3 V): if absent on 5 V: keyboard power glitches on keypress bursts.

6. Datasheet / protocol summary (PS/2)#

Device-clocked synchronous serial: the device generates CLK (~10–16.7 kHz); host and device both open-collector on CLK and DATA. 11-bit frames (start=0, 8 data LSB-first, odd parity, stop=1).
Power-on: keyboard runs a self-test and sends BAT code 0xAA (~0.5–0.75 s after power) — the canonical "keyboard is alive" event. Then it sends scan codes on keypress; the host can send commands (e.g. set LEDs) by pulling CLK low to inhibit, then clocking data out (host-to-device is the harder direction — the shifter must pass both ways).
5 V device logic; BSS138 shifters bridge to 3.3 V.

7. Expected values before bench testing#

Idle: CLK and DATA high on both sides (3.3 V on PMOD side, 5 V on device side).
~0.5–0.75 s after 5 V is applied, the keyboard clocks out 0xAA (BAT).
Keypress → 11-bit frames at ~10–16 kHz on CLK.

8. Manual review checklist#

[ ] Pigtail order verified (Section 4a); VCC to 5 V, not 3.3 V.
[ ] One BSS138 + two 10 k per line (CLK, DATA).
[ ] 3.3 V-side pull-ups to 3V3, 5 V-side pull-ups to 5 V.
[ ] Rails separate; decoupling on both.

9. Ordered bench-test procedure#

A. Unpowered: verify pigtail mapping, BSS138 orientation (source=3.3 V side), all four pull-ups and which rail each ties to; no rail short.

B. Rail sequence: 3.3 V first, then 5 V (≤200 mA). Confirm CLK/DATA idle high on both sides (scope both sides of one shifter — 3.3 V side ≤3.3 V, 5 V side ~5 V).

C. Shifter check: manually pull the 5 V side of DATA low; confirm the 3.3 V side follows low (device→host direction). Pull the 3.3 V side low; confirm the 5 V side follows (host→device direction). Both must work.

D. BAT code: attach a known keyboard; within ~0.75 s of 5 V, scope PMOD CLK/DATA and capture the 11-bit frame carrying 0xAA.

E. Keypress: press a key; confirm scan-code frames at ~10–16 kHz, correct start/parity/stop.

F. Host-to-device: issue a set-LEDs command (host pulls CLK low, clocks DATA); confirm the keyboard LEDs change — proves the bidirectional shift.

10. Troubleshooting map#

No 0xAA: no 5 V, wrong pigtail (VCC), or a dead shifter; check both-side idle levels first.
One-way only: a BSS138 missing/backwards, or a pull-up absent on one side.
Corrupted frames: pull-ups too large (slow edges) or noisy 5 V.
Keyboard damaged: VCC/GND swap (Section 4a not done).

11. Bench record template#

Board: axo-016  Pigtail order verified: [ ]
CLK/DATA idle both sides (3.3/5V): [ ]
Shifter both directions: [ ]
BAT 0xAA captured: [ ]  keypress frames OK: [ ]  set-LEDs works: [ ]
Notes:

12. Review conclusion#

The board is the BSS138 bidirectional shifter done twice; the must-verify items are the pigtail VCC/GND (Section 4a — a swap kills the keyboard) and that both shifters pass signals in both directions (host-to-device LED commands are the strict test). The 0xAA BAT code within ~0.75 s of 5 V is the alive signal.