← AXO-014

Circuit review & bench-test guide

AXO-014 — IR remote link PMOD module

Document purpose#

This document explains the axo-014-ir module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on generate_design.py, README.md, and reports/erc.rpt.

This board has never been fabricated or assembled. The schematic is ERC clean (0/0, see reports/erc.rpt) and the netlist has been reviewed, but the PCB layout has not been started — no gerbers, no renders, no physical board. Every number here is a design target or a datasheet expectation to verify. Layout-dependent items (RX shading from the TX LED's side lobe, emitter thermal spreading, supply-RC placement) cannot be reviewed yet and are flagged below.

1. What the board does#

AXO-014 carries both halves of an IR remote link so the NEC protocol can be taught in both directions on one PMOD:

• RX: a Vishay TSDP34138 38 kHz demodulating receiver strips the carrier and hands the FPGA a clean demodulated bitstream (idle high, active low when a 38 kHz burst is present) on PMOD pin 1.
• TX: the FPGA generates its own 38 kHz carrier on PMOD pin 2, gates it with NEC bursts, and drives a TSAL6400 940 nm emitter through an AO3400A N-channel low-side switch with a 33 Ω ballast (~57 mA peak).

It teaches nec_ir_rx (decode any TV remote) and nec_ir_tx (remote-control the actuator-line robot). It does not decode NEC in hardware — the FPGA does the timing/framing. The TX LED must be driven with the 38 kHz carrier, never DC-high.

Functional block diagram#

PMOD plug J1 (Type 1 GPIO)
  6/12: 3V3 ──┬── R1 47R ──┬── IR_VS ──┬── U1 Vs (TSDP34138)
              │            C1 10uF     C2 100nF
              │            (RC bulk)   (pin bypass)
              │            to GND      to GND
  1: IR_RX <── R2 100R ── IR_OUT ────── U1 OUT (push-pull, idle high)
              U1 GND ── GND

  6/12: 3V3 ── R3 33R (0805) ── LED_A ─[D1 TSAL6400]─ LED_K ── Q1 drain (AO3400A)
  2: IR_TX ── R4 1k ── IR_TX_G ──┬── Q1 gate         Q1 source ── GND
                                 └── R5 10k ── GND (gate pull-down)

2. Safety and scope boundaries#

• Electrically benign for the operator: 3.3 V rail, tens of mA peak. Standard ESD handling for the receiver.
• The emitter is invisible 940 nm light, not a hazard at this power (57 mA through a 5 mm LED), but do not stare into it through magnification for extended periods, and remember a phone camera is the cheapest "is it emitting?" check.
• Drive IR_TX with the carrier, never DC-high. A stuck-high IR_TX is electrically safe (57 mA peak < the LED's 100 mA continuous rating, so no duty cycle can destroy the part) but wastes ~190 mW continuously in the LED and ballast and floods the room, blinding every IR receiver nearby.
• The 33 Ω ballast is an 0805 deliberately: peak I²R ≈ (0.057)²·33 ≈ 107 mW exceeds an 0603's 100 mW rating; do not substitute an 0603.
• Use a current-limited 3.3 V bench supply (≤100 mA limit) for standalone tests. Continuous NEC traffic averages < 20 mA in the LED; a DC-high fault draws ~57 mA continuously.
• Never drive/back-drive any PMOD signal above VDD+0.3 V, including unpowered.

3. Power and signal sequence#

1. The host applies 3.3 V to PMOD 6/12 and GND to 5/11.
2. Receiver rail: R1 (47 Ω) + C1 (10 µF) + C2 (100 nF) form the datasheet application-circuit supply filter; IR_VS (a filtered node, not the raw rail) powers U1's Vs. The RC suppresses supply disturbance that would otherwise couple into the demodulator's AGC.
3. Receiver output: U1's OUT is push-pull (verified: the stock symbol types pin 1 as output, matching the TSDP341xx push-pull driver — unlike TSOP parts that need an external pull-up). It idles high and pulses low under a valid 38 kHz burst; R2 (100 Ω) series-protects it into PMOD 1.
4. Emitter default-off: R5 (10 kΩ) pulls Q1's gate to GND, so the emitter is off while the host pin is unconfigured. R4 (1 kΩ) is the gate series resistor from PMOD 2.
5. Emitter drive: the host toggles IR_TX with a 38 kHz carrier; Q1 turns on each carrier half-cycle, sinking LED current set by R3: I ≈ (3.3 − V_F(TSAL6400 ≈ 1.35 V) − I·Rds(on)(AO3400A ≈ 30 mΩ)) / 33 Ω ≈ 57 mA peak. NEC bursts gate the carrier so average LED current stays < 20 mA.

4. Interfaces#

• IR_RX: demodulated receiver output, idle high, active low, push-pull through R2.
• IR_TX: emitter gate drive; must carry the 38 kHz carrier gated by NEC bursts. Active high (drives the gate high to turn the LED on).

NEC framing the HDL must produce/decode: 9 ms AGC burst + 4.5 ms space, then 32 bits (address / ~address / command / ~command), each bit a 562.5 µs burst then a 562.5 µs space (logic 0) or 1.6875 ms space (logic 1), all bursts being 38 kHz carrier at ~50 % duty.

No dedicated test points; probe at J1 and the R1–R5/C1–C2/D1/Q1 pads. (Layout to-do: add probe pads; keep RX shaded from the TX side lobe.)

5. Component-by-component review#

5.1 Receiver#

5.2 Receiver supply filter and output series#

5.3 Emitter#

Power flags #FLG01 (3V3), #FLG02 (GND), and #FLG03 (IR_VS — the filtered node needs its own ERC source marker since it is fed through R1) are ERC markers, not physical parts. Every schematic reference designator (U1, D1, Q1, J1, R1–R5, C1–C2) is covered. No jumpers on this module.

6. Datasheet summary and design interpretation#

Primary references: Vishay TSDP341xx, TSAL6400, AO3400A. Check revisions before procurement.

Emitter current math (design): I = (3.3 − 1.35 − I·0.03)/33 ≈ 57 mA peak. NEC at 50 % carrier duty gated by bursts → average LED current < 20 mA. A DC-high IR_TX dissipates ~190 mW (LED + ballast) — safe but wrong.

7. Expected values before bench testing#

None measured — no board exists.

The canonical first checks#

Receiver: power the board, scope PMOD 1 — idle 3.3 V. Point any TV remote at U1 and press a button: PMOD 1 should show the NEC envelope (a long ~9 ms low AGC pulse, then the bit pattern of low bursts). This is the nec_ir_rx input. No response = U1 unpowered (R1 open), wrong carrier, or R2 open.

Emitter: with the LED driven by a 38 kHz square wave (bench function generator or the HDL carrier), a phone camera pointed at D1 shows a flickering white/purple glow. Scope across R3 shows ~38 kHz pulses; the voltage across R3 divided by 33 Ω is the peak current (≈57 mA). A DC-high test should be brief only — it is safe but pointless.

8. Manual schematic and assembly review checklist#

Reviewable now:

• U1 pin map vs TSDP341xx (Vishay MOLD-3Pin): OUT(1), GND(2), Vs(3) — confirm Vs is on IR_VS (filtered), GND to GND, OUT to R2. A Vs/GND swap is fatal.
• Confirm the RX output has no external pull-up (push-pull part) and OUT passes only the 100 Ω R2.
• Confirm Q1 pinout: AO3400A SOT-23 gate(1)/source(2)/drain(3); source to GND, drain to LED_K, gate to IR_TX_G. A swapped source/drain breaks switching.
• Confirm D1 polarity: anode to R3 (LED_A), cathode to Q1 drain (LED_K).
• Confirm R3 is the 0805 (not 0603) for the I²R rating.
• Re-run ERC after regeneration (clean today).

Assembly (eventual first article — none exists yet):

• J1 pin-1/zigzag vs the PMOD spec and a physical socket.
• Measure R1–R5; confirm C1/C2 close to U1 Vs.
• Layout: RX shaded from the TX LED's side lobe (or crosstalk defeats loopback tests); both optical parts at the board edge; emitter copper for heat spreading.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, supply voltage, equipment, and operator. Contexts: standalone (bench supply + function generator / SPI-free GPIO source, phases B–D) and PMOD host (FPGA drives the carrier and decodes, phase E).

A. Unpowered inspection and resistance tests#

1. Complete the Section 8 checklist under magnification.
2. DMM 3V3-to-GND (J1 6 → 5), both polarities: no hard short.
3. IR_VS → 3V3: ≈47 Ω (R1). IR_TX_G → GND: ≈10 kΩ (R5).
4. Diode-mode across R3+D1 (LED_A → LED_K): a diode drop plus the ballast; reverse reads open. Confirms D1 polarity.
5. IR_RX (PMOD 1) → U1 OUT: ≈100 Ω (R2).

B. Standalone first power (receiver)#

1. Bench supply 3.3 V (measure it), current limit 50–100 mA, output off. Wire + to J1 6/12, − to 5/11.
2. Power on: no trip; quiescent draw ≈ sub-mA. Verify IR_VS ≈ 3.3 V (small drop across R1), C1/C2 charged.
3. Scope PMOD 1: idle high (≈3.3 V).

C. Receiver 38 kHz burst capture and NEC decode#

1. Point any 38 kHz NEC remote (most TV remotes) at U1; press a button.
2. Scope PMOD 1: confirm the 9 ms AGC low burst + 4.5 ms high space, then 32 bit-cells (each a 562.5 µs low burst followed by a 562.5 µs or 1.6875 ms high space). Idle returns high.
3. Decode by hand or with a logic analyzer's IR decoder: the 32 bits are address / ~address / command / ~command; ~address should be the bitwise complement of address (a quick sanity check that framing is right).
4. Vary distance/angle; confirm reliable demod within the receiver's range. Erratic/false low pulses point at a weak supply RC (C1) or ambient IR.

D. Emitter drive and current verification (duty limits)#

1. Drive IR_TX from a function generator: 38 kHz square wave, 50 % duty, 3.3 V amplitude (never DC-high for the current-verification step beyond a momentary check).
2. Scope across R3: pulses at 38 kHz; peak V_R3 / 33 Ω ≈ 57 mA peak. Confirm the average is much lower under gated bursts.
3. Phone camera on D1: visible flicker confirms emission.
4. Duty-limit note to record: peak 57 mA < 100 mA continuous, so no NEC duty pattern can overstress the LED; the only limit is thermal on R3 (0805, ~107 mW peak) and decode etiquette (don't flood the room). A brief DC-high test (≤ a few seconds) verifies the LED lights continuously and Q1 stays cool, then return to carrier drive.

E. PMOD-host loopback (FPGA carrier + decode)#

1. Measure the host socket rail: 3.3 V. Plug in with the host unconfigured; verify IR_TX_G near 0 V (R5 holding Q1 off).
2. Load nec_ir_tx: generate a 38 kHz carrier gated by a known NEC frame on IR_TX. Scope PMOD 2 and R3 to confirm the carrier and current.
3. Load nec_ir_rx on IR_RX. Loopback: aim the emitter at (or reflect it toward) the receiver; the decoded address/command out of nec_ir_rx should equal what nec_ir_tx sent. This is the module's headline test.
4. If the RX sees the TX even without line-of-sight (crosstalk), the layout shading is inadequate — record it as a layout finding.
5. Range/interoperability: decode several real remotes; transmit to a consumer IR device or the actuator-line robot receiver.

F. Release-only tests#

Optical power/wavelength characterization, thermal soak of R3/D1 at worst duty, ESD at J1 and the exposed emitter, and RX sensitivity/interference testing belong to a separate qualification plan, gated on a board existing.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The schematic is a faithful two-halves IR link: a push-pull TSDP34138 with the datasheet's 47 Ω + ≥ 4.7 µF supply RC and a 100 Ω output series resistor, and a TSAL6400 low-side-switched by an AO3400A behind a 33 Ω 0805 ballast that sets a ~57 mA peak, with a gate pull-down guaranteeing emitter-off before configuration. The current math is stated and safe (57 mA < 100 mA continuous, so no duty cycle can destroy the LED), the 0805 ballast choice is justified by I²R, and the "carrier not DC" rule is the operational discipline that matters. The principal risks are that nothing physical exists yet (no layout, no first-article data); TX/RX optical crosstalk that only a real layout with RX shading can resolve; and correct AO3400A/D1 orientation and the 0805 ballast at assembly. The bring-up ladder — RX NEC envelope capture, real- remote decode, emitter current verification with duty note, and the FPGA carrier→decode loopback — is exactly what the nec_ir_rx/nec_ir_tx cores will need to reproduce.