I/O modules

AXO-012 — 4×4 matrix keypad interface PMOD module

Catalog #12 in the AruviX output line, level L2. Interface board for the ubiquitous 8-pin 4×4 membrane keypad (its ribbon plugs into J2).

Circuit review & bench-test guide →

Components#

Every placed component, with the reason it is on the board. Extracted directly from the schematic, so this cannot drift from the design.

Signals#

Net labels used in the schematic, which are also the names the HDL top level should use.

3V3 COL1 COL1_K COL2 COL2_K COL3 COL3_K COL4 COL4_K GND ROW1 ROW1_K ROW2 ROW2_K ROW3 ROW3_K ROW4 ROW4_K

Production status#

Source: boards/io-modules/axo-012-keypad

Catalog #12 in the AruviX output line (../README.md), level L2. Interface board for the ubiquitous 8-pin 4×4 membrane keypad (its ribbon plugs into J2).

Status: schematic generated, ERC clean (0/0), netlist reviewed. PCB layout not started. Not released.

What it teaches#

Matrix scanning (keypad_scan HDL core): drive one row low at a time, read the four pulled-up columns — a low column identifies the key at (row, col). Rotate at ~1 kHz; debounce in fabric by reusing the sensor-line debounce core (membrane domes bounce for milliseconds; the line rule is HDL debounce, not RC-only). Ghosting/rollover limits of a diode-less matrix are part of the lesson.

Design#

• J2 = 1×08 pin socket, common membrane pinout: pins 1–4 = ROW1–4, 5–8 = COL1–4 (pin 1 leftmost with the keypad face up).
• 100 Ω series resistors on ALL 8 lines, not just the module-driven columns: the ribbon is unkeyed, so a shifted or reversed plug-in can connect a host-driven row output to another driven line — 100 Ω both ways bounds any miswire current (documented on the schematic).
• 10 k pull-ups on the four column (read) lines, keypad side.
• ESD arrays, DNP: the catalog allowed a skip, but a stock 4-channel TVS array does exist — Power_Protection:CDSOT236-0504C (Bourns, SRV05-4 family, SOT-23-6, stock footprint). Two are placed DNP (D1 rows, D2 columns) on the keypad side; fit them for a harsh-ESD classroom build.

PMOD pin map (Type 1 GPIO)#

Rows = host outputs (one low at a time); columns = host inputs (idle high).

Regenerate#

python3 generate_design.py

Remaining for release#

• [ ] PCB layout (J2 at the board edge for the ribbon, silkscreen ROW/COL map), DRC, fab outputs
• [ ] hdl/: instantiate keypad_scan + debounce, keycode demo
• [ ] BOM export and availability check, design-review checklist