Circuit review & bench-test guide

AXO-011 — MAX98357A I2S class-D amplifier PMOD module

Design-stage — board not yet fabricated

Document purpose#

Component-level explanation and bench-test plan for axo-011-i2s-amp, from generate_design.py, the module README.md, and the MAX98357A datasheet. Never fabricated; values are verification targets. This board completes the audio path the I2S mics started: record → filter in fabric → play back.

1. What the board does#

A mono I2S-input class-D speaker amplifier. The host generates I2S (LRCLK, BCLK, DIN); the MAX98357A decodes it, applies a selectable channel/gain, and drives a speaker terminal directly (filterless class-D). Runs from PMOD 3.3 V.

PMOD J1  LRCLK/DIN/BCLK (Type 7: 1/2/4) ─> U1 MAX98357A ─> J2 speaker (4-8R)
         SD_MODE strap (JP1) = channel/shutdown ; GAIN strap (JP2)

2. Safety and scope boundaries#

3.3 V only. PMOD host or 3.3 V bench supply. Class-D output current can spike — set the bench limit ~1 A, use a real 4–8 Ω speaker (not a short).
At 3.3 V the amp delivers ~1.4 W into 4 Ω (vs 3.2 W at 5 V) — documented; the board is intentionally 3.3 V-only, no external rail.
Filterless class-D output is a ~300 kHz PWM waveform: do not scope it expecting clean audio without the speaker's inductance as the filter, and keep leads short (EMI).
Unreleased prototype.

4. Interfaces#

J1 PMOD Type 7 I2S (per the platform spec notes): 1 LRCLK, 2 DIN (DAC/host-driven data), 4 BCLK, 5/11 GND, 6/12 3V3. The host is the I2S controller.
J2 speaker terminal (4–8 Ω).
JP1 SD_MODE strap: channel select / shutdown. JP2 GAIN strap.

5. Component-by-component review#

U1 MAX98357A (TQFN-16): I2S DAC + 3.2 W class-D amp. Decodes standard I2S (16–32 bit, 8–96 kHz), auto-detects sample rate from BCLK/LRCLK. If absent: no output. If BCLK/LRCLK/DIN framing is wrong: silence or noise — I2S must be well-formed (the mics teach the same framing).
SD_MODE (JP1) + divider: this single pin does triple duty via a resistor divider against the chip's internal 100 kΩ pull-down: shutdown (< 0.16 V), (L+R)/2 (~0.30 V, the default here), right-only (~0.77 V), left-only (> 1.4 V). The board's default divider targets ~0.30 V = mono mix. If the divider is wrong or SD_MODE floats: the chip may sit in shutdown (silent) — the most common "dead amp" cause. Verify ~0.30 V at SD_MODE.
GAIN (JP2) strap: selects 3/6/9/12/15 dB per the datasheet (float = 9 dB default). If mis-strapped: wrong loudness, or with a hard tie the wrong code.
R1 (100 Ω / straps): part of the SD_MODE/GAIN strap network. If a strap resistor is wrong: mode/gain misread.
C1 100 nF + C2 (bulk): supply decoupling. Class-D draws pulsed current; if bulk absent: audible supply sag/distortion at volume.

6. Datasheet summary (MAX98357A)#

VDD 2.5–5.5 V; output 3.2 W into 4 Ω at 5 V, ~1.4 W at 3.3 V. Filterless class-D, ~300 kHz.
I2S: standard/left-justified, auto sample-rate 8–96 kHz, BCLK 16/32× fs.
SD_MODE analog-multiplexed pin (shutdown / mono / right / left) via the external divider vs an internal 100 kΩ pull-down.
GAIN pin: 5 levels by tie to GND/VDD/float/resistor.
Click-and-pop suppression, thermal + short-circuit protection built in.

7. Expected values before bench testing#

SD_MODE ≈ 0.30 V (mono mix, not shutdown).
With a valid I2S stream of a sine, a 4–8 Ω speaker plays audibly; supply draws a few hundred mA at moderate volume.
No I2S clock → silence (not noise).

8. Manual review checklist#

[ ] Type 7 map: LRCLK=1, DIN=2, BCLK=4.
[ ] SD_MODE divider targets ~0.30 V (measure — must not be < 0.16 V shutdown).
[ ] GAIN strap at intended level.
[ ] Speaker terminal is 4–8 Ω rated; decoupling present.

9. Ordered bench-test procedure#

A. Unpowered: verify I2S pin map, SD_MODE divider resistors, GAIN strap, speaker terminal; no rail short.

B. Power, no clock: 3.3 V (~1 A limit). Measure SD_MODE ≈ 0.30 V (critical — confirms not-shutdown). Output silent (no I2S) — expected.

C. I2S bring-up: host emits a 1 kHz sine over I2S (e.g. 48 kHz/16-bit). Speaker should play a clean tone. Confirm the amp auto-locked to the sample rate.

D. Framing scope: scope LRCLK/BCLK/DIN together; confirm BCLK = 32× (or 64×) LRCLK and DIN aligned to the standard I2S one-BCLK delay after the WS edge.

E. Gain check: change the GAIN strap (or its resistor) and confirm the loudness step; verify against the datasheet dB table.

F. Protection: briefly reduce speaker load / warm the part; confirm thermal/ short protection mutes rather than damages (do gently). Confirm click-pop suppression on enable.

10. Troubleshooting map#

Silent with valid I2S: SD_MODE in shutdown (< 0.16 V) — measure and fix the divider FIRST. Then check I2S framing.
Noise not tone: malformed I2S (BCLK/LRCLK ratio, bit alignment).
Distortion at volume: supply sag — bulk decoupling / current limit; or 3.3 V power ceiling reached (~1.4 W).

11. Bench record template#

Board: axo-011  SD_MODE voltage: __ V (target 0.30)
1kHz tone audible: [ ]   Auto sample-rate lock: [ ]
I2S framing correct on scope: [ ]   Gain step verified: [ ]
Notes:

12. Review conclusion#

The one measurement that matters first is SD_MODE ≈ 0.30 V — a wrong divider parks the amp in shutdown and mimics a dead board. After that it's standard I2S: the same framing the mic modules produce, now consumed. The 3.3 V-only power ceiling (~1.4 W) is a deliberate scope choice, not a defect.