← AXO-008

Circuit review & bench-test guide

AXO-008 — ST7735 1.8" SPI TFT carrier PMOD module

Document purpose#

This document explains the axo-008-tft carrier at component level and turns the design evidence into a manual-review and bench-test plan. It is based on generate_design.py (rev 0.1-schematic, 2026-07-12), the README, the generated schematic, the ERC report (reports/erc.rpt), and well-known Sitronix ST7735/ ST7735S facts. The ST7735S datasheet is not in the local cache and was not fetched for this revision; every controller fact below is reasoned from the README plus common ST7735 knowledge and must be re-checked against Sitronix's datasheet before release.

The board is an unfabricated prototype: schematic generated, ERC clean (0 errors / 0 warnings), netlist reviewed, no PCB layout, no fabricated board, no BOM export, no bench results. The J2 socket MPN is TBD:. The plug-in is the ubiquitous 1.8" 128×160 ST7735 SPI TFT breakout — an uncontrolled commodity part whose pinout varies between clones, so carrier validation is only meaningful against a specific purchased unit. Every expected value below is a design target to verify, not proof that an assembled board works.

1. What the board does#

The carrier hosts a common 1.8" 128×160 ST7735 SPI TFT breakout on a 1×8 socket (J2) and fans it out to a single PMOD Type 2A (SPI) plug (J1) on the ECP5 host. It is a write-only display interface: the FPGA sends init commands and RGB565 pixels over 4-wire SPI, framing each byte as command or data with the D/C (A0) line, and races the beam with no framebuffer chip in the path. There is no readback — the ST7735's MISO/read path is not brought out on the common breakout, so PMOD pin 3 is NC.

The backlight LED is driven through a 100 Ω series resistor (R3) from a 3-pad solder jumper (JP1) that selects either always-on 3V3 (default) or PWM dimming from PMOD pin 9. Idle-safety pull-ups hold ~RESET and ~CS in a defined state until the host takes over. Nothing here is display-quality qualification: color fidelity, viewing angle, and panel uniformity are commodity-breakout properties, not carrier properties.

Functional block diagram#

PMOD Type 2A (J1)                          ST7735 breakout (J2, 1x8)
  1  ~CS   ──┬── R2 10k ── 3V3 ──────────  3 CS
  2  MOSI(SDA) ──────────────────────────  6 SDA
  3  NC  (no MISO - write-only display)
  4  SCK  ───────────────────────────────  7 SCK
  7  DC (A0: data/command) ───────────────  5 A0/DC
  8  ~RST  ──┬── R1 10k ── 3V3 ───────────  4 RESET
  9  BL_PWM ─┐
             ├ JP1 [1-2 def: 3V3 | 2-3: PWM] ── R3 100R ── 8 LED
  6/12 3V3 ──┴─ C1 100nF ─ C2 10uF ─ GND ─  1 VCC
  5/11 GND ──────────────────────────────  2 GND

2. Safety and scope boundaries#

• Single 3.3 V domain, no external supply: electrical risk is low. The real hazard is orientation/pin-order error on an unkeyed 1×8 socket (section 4). A reversed insertion or a swapped-order clone puts 3V3 and GND on the wrong breakout pins and can destroy the display.
• The breakout expects 3.3 V logic. Do not plug this carrier into a 5 V PMOD host; the ST7735 and most breakout LDOs are not 5 V-tolerant on the logic pins.
• Standalone bench work uses a current-limited 3.3 V supply (limit ~100 mA; the display plus backlight at ~20 mA draws well under that).
• Earth-referenced oscilloscope grounds clip only to board GND.
• The backlight path can draw ~20 mA continuously; JP1 mis-set to bridge all three pads shorts 3V3 to PMOD pin 9 — verify JP1 before power (section 4.3).
• A picture on the screen is not an EMC, ESD, or environmental qualification. Do not infer panel or carrier robustness from a working demo.

3. Power and control sequence (design intent + SPI init summary)#

At the carrier level the sequence reduces to power ordering plus the ST7735 bring-up the host must perform:

1. Host powers the PMOD (3V3 on pins 6/12, GND on 5/11). C1/C2 decouple the socket. R1 holds ~RESET high (display out of reset by default) and R2 holds ~CS high (bus idle, no garbage clocked in) until the host drives them.
2. The backlight follows JP1: default 1-2 lights the LED from 3V3 through R3 immediately at power-up; 2-3 leaves it dark until the host drives PMOD pin 9.
3. Hardware reset: pulse ~RESET (PMOD pin 8) low ≥10 µs, release, then wait ≥120 ms before the first command. This is the reliable cold-start path even though R1 already holds the part out of reset.
4. SPI init (write-only, 4-wire, mode 0): SCK idles low, D/C (A0) low = command byte, D/C high = data byte, ~CS low frames each transaction. The standard ST7735 bring-up ordered command list:

• SWRESET (0x01) — software reset, wait 120 ms.
• SLPOUT (0x11) — sleep out, wait 120 ms.
• FRMCTR1/2/3 (0xB1/B2/B3) and PWCTR1..6 — frame-rate and power control (panel-specific values from the breakout's reference init).
• COLMOD (0x3A) = 0x05 — 16-bit/pixel RGB565 color mode.
• MADCTL (0x36) — memory access control: sets row/column order, scan direction, and RGB-vs-BGR panel order (the two knobs clones differ on).
• INVOFF/INVON (0x20/0x21) as the panel requires.
• CASET (0x2A) / RASET (0x2B) — column and row address windows.
• DISPON (0x29) — display on.

1. Draw: set the window with CASET/RASET, issue RAMWR (0x2C), then stream RGB565 bytes (two per pixel) with D/C high. There is no readback path on the breakout, so the host must track state itself.

Maximum SCK on this design is treated as ~15 MHz per the README; confirm the panel's write-cycle timing against the Sitronix datasheet before pushing the clock. The FPGA must constrain SCK/MOSI/DC skew accordingly.

4. Plug-in module verification (read before first power)#

Mandatory section. 1.8" ST7735 breakouts are mostly-but-not-always identical, the socket is an unkeyed 1×8 that accepts a reversed module, and some clones swap VCC/GND or move the LED pin. This is the load-bearing per-unit check — getting it wrong can put 3V3 on GND or reverse the whole strip.

4.1 Pin-order check against the breakout silkscreen#

The carrier assumes the most common top-down 1×8 order:

Procedure — breakout unplugged and carrier unpowered:

1. Read the breakout's silkscreen for all 8 positions and write them down. Known variants swap VCC/GND (pin 1/2), and some move LED away from pin 8. Do not assume; transcribe the actual legend.
2. Buzz the breakout's own VCC pin to its LDO/backlight-driver input and GND to its ground pour to confirm which end is pin 1 (VCC) versus pin 2 (GND).
3. On the carrier, buzz J2 pin 1 to the PMOD 3V3 pins (6/12) and J2 pin 2 to GND (5/11); then confirm the breakout's power pair lands there in the actual insertion orientation. The 1×8 socket is unkeyed and will physically accept a 180°-flipped module — mark the correct orientation on both boards.
4. Spot-check the five signal pins end-to-end before soldering the socket or plugging in: CS to J2 pin 3 (through the R2 node), RESET to J2 pin 4 (through the R1 node), A0/DC to J2 pin 5, SDA to J2 pin 6, SCK to J2 pin 7.
5. If the silkscreen shows a VCC/GND-swapped clone, either re-solder the socket to match that unit or do not use it — plugging a swapped clone into the assumed-order socket applies GND to VCC and 3V3 to GND. Record the decision.
6. Only then power up.

4.2 Plug-in key specifications (ST7735/ST7735S, reasoned from README + knowledge)#

Because the read path is not present, the AruviX family's "100 Ω on module-driven lines" rule has no lines to apply to here — every SPI line is host-driven. R3's 100 Ω is a backlight LED current limiter, not a series-termination resistor.

4.3 Backlight jumper (JP1) verification#

Before first power, inspect JP1's solder bridge and confirm the intended position:

• 1-2 (default, factory-bridged): LED pin ← R3 ← 3V3, always on (~20 mA). Backlight lights immediately at power-up. Verify pads 1-2 bridged and 2-3 open.
• 2-3 (PWM): cut 1-2, bridge 2-3. LED pin ← R3 ← PMOD pin 9 (BL_PWM). The backlight is dark until the host drives pin 9 — a dark screen with correct SPI is expected here, not a fault.
• Failure modes: all three pads bridged shorts 3V3 to PMOD pin 9 (drive contention/short); no pads bridged leaves the backlight permanently dark regardless of host state.

Verify on the bench by measuring the R3 breakout-side node: ~3.3 V minus the R3 drop in 1-2 mode with backlight lit; following the PMOD-pin-9 duty cycle in 2-3 mode.

5. Component-by-component review#

Every reference designator in generate_design.py appears below. #FLG01 and #FLG02 are ERC power-flag pseudo-components on 3V3 and GND; they have no physical footprint and are listed only for completeness.

6. Datasheet summary and design interpretation#

No datasheet was fetched for this revision — the ST7735S datasheet is not in the local cache. Confirm the exact init sequence, max SCK write-cycle time, and MADCTL bit definitions against Sitronix's datasheet (and the specific breakout vendor's reference init) before release.

7. Expected values before bench testing#

All are design targets assuming 3V3 = 3.300 V, not measured results.

8. Manual schematic and assembly review checklist#

• Complete section 4.1 (pin order) against the purchased breakout before soldering the socket; record the silkscreen map and orientation in the repo.
• Confirm JP1 is bridged 1-2 (or the intended PWM 2-3) and never all-three bridged (section 4.3).
• Measure R1 = 10 k (~RESET to 3V3), R2 = 10 k (~CS to 3V3), R3 = 100 Ω (BL_SRC to LED pin).
• Confirm C1/C2 are placed close to the socket power pins during layout review (layout not yet started — carry forward).
• Verify J1 pin-1 orientation against Pmod spec 1.2 (family placement recipe in pmod-common/PMOD-SPEC-NOTES.md); confirm pin 3 and pin 10 are NC.
• Confirm the socket is unkeyed and mark the correct insertion orientation on the silkscreen with the pin-order map (README release item).
• Close the TBD: J2 socket MPN; export and availability-check the BOM.
• Plan FPGA constraints: SCK ≤15 MHz, MOSI/DC skew relative to SCK, and a clean ≥120 ms reset delay in the init FSM.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host identity, the purchased breakout's silkscreen map and orientation, JP1 state, SCK frequency, and measured 3V3.

Two contexts throughout: (a) PMOD host — plug into a 3.3 V PMOD port on the ECP5 host (ULX3S-class) driving the ST7735 init/draw core; (b) standalone 3.3 V bench — wire 3V3/GND from a current-limited supply and CS/MOSI/SCK/DC/ RST/BL to a 3.3 V SPI adapter (Pi Pico, FT2232H, Bus Pirate) running a known ST7735 library.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 checklist and the section 4.1 buzz-out/orientation marking under magnification (socket empty).
2. Measure 3V3-to-GND resistance in both meter polarities; investigate < 1 kΩ before applying power.
3. Confirm R1 (~RESET) and R2 (~CS) each read ~10 kΩ to 3V3, and R3 reads ~100 Ω from BL_SRC to the LED pin.
4. Verify JP1 continuity: bridged 1-2 (default) means 3V3 reaches BL_SRC; 2-3 means PMOD pin 9 reaches BL_SRC. Confirm all three pads are not bridged.

B. First power, no SPI traffic#

1. With the breakout socketed in the verified orientation, apply power (context a or b). Watch the current limit.
2. Measure 3V3 at J2 pin 1 and 0 V at J2 pin 2. Measure supply current.
3. Confirm ~RESET and ~CS both sit near 3.3 V (pull-ups working, host tristated).
4. Backlight: in JP1 1-2 the backlight should light immediately (~20 mA rail delta); in JP1 2-3 it stays dark until pin 9 is driven — confirm the expected behavior for the fitted jumper before suspecting a fault.

C. Reset and SPI framing#

1. Pulse ~RESET (PMOD pin 8) low ≥10 µs, release, wait ≥120 ms. Scope the pulse at J2 pin 4.
2. On a logic analyzer at the socket, confirm SCK idles low (mode 0), ~CS frames each transaction low, and D/C (A0) is low during the first command bytes. This proves the framing line before any pixels.
3. Send SWRESET (0x01), wait 120 ms; SLPOUT (0x11), wait 120 ms. No visible change yet (display still off) — this only proves the write path clocks.

D. Init sequence and first pixels#

1. Run the full init: FRMCTR/PWCTR (breakout reference values), COLMOD = 0x05 (RGB565), MADCTL (start with the vendor library's value), INV as required, DISPON (0x29).
2. Set a full-screen window (CASET 0x2A / RASET 0x2B for 128×160), issue RAMWR (0x2C), and stream a solid color fill (two RGB565 bytes/pixel, D/C high). Expect a uniform screen in the commanded color.
3. Color order check: fill pure red, green, blue in turn. If red and blue are swapped, the panel is BGR rather than RGB — flip the MADCTL RGB/BGR bit and re-test. This is the most common per-clone difference.
4. Orientation check: draw an asymmetric pattern (e.g., a filled corner marker) and confirm origin/rotation match your MADCTL choice; adjust the row/column/exchange bits as needed and record the final MADCTL value for this breakout.

E. Draw performance and backlight control#

1. Push a full-frame animation at the target SCK (up to ~15 MHz). Confirm no tearing artifacts beyond the expected framebuffer-less beam race, and that MOSI/DC hold against SCK at rate (widen the clock constraint if bytes drop).
2. Backlight PWM (only if JP1 is 2-3): drive PMOD pin 9 with a PWM waveform and confirm brightness tracks duty cycle; scope the R3 breakout-side node. In JP1 1-2 the backlight is fixed-on and pin 9 has no effect — expected.
3. 30-minute soak: continuous draw, confirm the image is stable, rail current steady, and socket/backlight temperature reasonable.

F. Release-only tests#

Panel color/uniformity grading, EMC, ESD, and long-cable SPI integrity are out of scope for the first article and require controlled plans. The TBD: socket MPN and BOM availability must be closed before any production release.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design is a clean minimal ST7735 carrier: a single PMOD Type 2A SPI plug, idle-safety pull-ups on ~RESET and ~CS, a backlight source-select jumper with a 100 Ω current limit, and socket decoupling. Because the breakout exposes no read path, every SPI line is host-driven and the family's 100 Ω module-driven-line rule correctly has nothing to apply to — a fact the design states rather than silently omits. The datasheet-anchored constants (RGB565 COLMOD 0x05, mode-0 SPI, ~120 ms reset, the SWRESET→SLPOUT→COLMOD→MADCTL→DISPON init) give the bench plan objective bring-up gates. The principal risks are (1) the unkeyed 1×8 socket and the VCC/GND-swapped clone problem, which make the per-unit pin-order check (section 4) load-bearing; (2) MADCTL RGB/BGR and orientation defaults that vary per breakout and must be found empirically; (3) everything layout-dependent — socket orientation silkscreen, decoupling placement, SCK integrity — which exists only as intent today; and (4) the absence of any fabrication, BOM export, HDL core, or bench evidence at this revision, plus a TBD: socket MPN and a controller datasheet that was reasoned from knowledge rather than fetched.