Circuit review & bench-test guide

AXO-005 — LCD1602 character LCD PMOD module

Design-stage — board not yet fabricated

Document purpose#

Component-level explanation and bench-test plan for axo-005-lcd1602, from generate_design.py, the module README.md, and the WC1602A/HD44780 and SN74AHCT541 datasheets. Never fabricated; values are verification targets. A mixed-voltage board (5 V LCD, 3.3 V host) — read the sequencing notes.

1. What the board does#

Drives a standard 16×2 HD44780 character LCD in 4-bit mode. The LCD runs at 5 V; its logic VIH (0.7·VDD = 3.5 V) exceeds the FPGA's 3.3 V, so RS/E/D4–D7 are buffered up through a 74AHCT541. R/W is grounded (write-only) so no 5 V signal ever returns toward the host.

PMOD J1  RS/E/D4-D7 ─> U2 74AHCT541 (3.3->5V, VCC=5V) ─> U1 WC1602A
EXT 5V J2 ─> U1 VDD, U2 VCC, backlight ; contrast trimmer -> U1 VO ; R/W -> GND

2. Safety and scope boundaries#

Two rails: 3.3 V logic (PMOD), 5 V (J2, LCD + buffer + backlight). Bring up 3.3 V first, then 5 V.
Standalone: 3.3 V into 3V3/GND and 5 V into J2, current-limited (~300 mA covers the backlight).
R/W is hard-grounded — the LCD never drives the bus, so busy-flag polling is unavailable; use fixed delays (documented design choice).
Unreleased prototype.

4. Interfaces#

J1 PMOD: 1 RS, 2 E, 3 D4, 4 D5, 7 D6, 8 D7, 5/11 GND, 6/12 3V3. All host-driven (write-only), buffered by U2.
J2 external 5 V + GND.
Contrast trimmer (VO), backlight jumper.

5. Component-by-component review#

U1 WC1602A (HD44780-compatible 16×2): the display. 4-bit interface here (D4–D7). If VO isn't set: blank or all-black — the #1 "dead display" cause is contrast, not a fault. If E never pulses: no writes register.
U2 74AHCT541 (SOIC-20, octal buffer): 3.3→5 V level shift on all six control/data lines (one 8-bit buffer covers RS/E/D4–D7 with room to spare). AHCT TTL inputs accept 3.3 V; VCC=5 V output meets the HD44780 VIH. If absent: the LCD may not see valid highs (blank/garbage). If ~OE pins float high: outputs hi-Z, LCD inputs float.
Contrast trimmer (10 k, TC33X): sets VO. If wiper open: uncontrolled contrast. Set for readable characters (VO ≈ 0.5–1 V typical).
D4–D7 net labels are the data lines (not diodes) — buffered through U2.
Backlight series resistor + jumper: limits the ~4.2 V/120 mA backlight from 5 V; cut-to-disable jumper. If shorted (no resistor): backlight over-current.
Decoupling 100 nF: on VDD. If absent: init glitches.

6. Datasheet summary (HD44780 / WC1602A)#

VDD 4.7–5.3 V (5 V part; 3.3 V variants exist but this board targets 5 V). Logic VIH = 0.7·VDD ≈ 3.5 V — the reason for the buffer.
4-bit init sequence (power-on): wait >40 ms, write 0x3 three times (with delays), then 0x2 (4-bit), then Function Set 0x28, Display Off 0x08, Clear 0x01 (>1.5 ms), Entry Mode 0x06, Display On 0x0C. E pulses latch each nibble.
Contrast via VO; backlight is an independent LED.

74AHCT541: VCC 4.5–5.5 V, TTL inputs, 8 buffered lines, two ~OE.

7. Expected values before bench testing#

Contrast set: a faint row of blocks visible even before init (row 1).
After the 4-bit init + "HELLO": legible characters.
U2 outputs swing 0→5 V; R/W stays at 0 V.

8. Manual review checklist#

[ ] R/W tied to GND (write-only).
[ ] U2 on all six lines; VCC = 5 V; ~OE tied active.
[ ] Contrast trimmer wired VDD/VO/GND.
[ ] Backlight resistor present; jumper default.
[ ] Rails separate, 3.3 V before 5 V.

9. Ordered bench-test procedure#

A. Unpowered: confirm R/W→GND, buffer path host→U2→U1, contrast trimmer connection, backlight resistor; no rail short.

B. Rail sequence + contrast: 3.3 V first, then 5 V. Adjust the trimmer until row 1 shows faint blocks — this alone proves the LCD is powered and contrast is in range.

C. Buffer scope: toggle E from the host; scope U2 input (3.3 V) and output (5 V); confirm clean 5 V edges.

D. Init + text: run the 4-bit init sequence with proper delays; write "HELLO WORLD"; confirm legible characters. (No busy-flag — use datasheet delays.)

E. Cursor/DDRAM: set DDRAM address to line 2 (0xC0); write text; confirm second-row addressing.

F. Backlight: toggle the backlight jumper/enable; confirm on/off and measure backlight current (~120 mA nominal).

10. Troubleshooting map#

Blank but backlit: contrast (VO) — adjust trimmer first, always.
Garbage/half characters: init sequence timing, or buffer missing (VIH).
Nothing at all: 5 V rail, or E not pulsing.
No second row: DDRAM address (0xC0) in firmware.

11. Bench record template#

Board: axo-005  Contrast blocks visible: [ ]  VO: __ V
U2 output swing: __ V   R/W at GND: [ ]
"HELLO" legible: [ ]   Line-2 addressing OK: [ ]
Backlight current: ____ mA
Notes:

12. Review conclusion#

The engineering content is (1) the 5 V buffer, needed because HD44780 VIH exceeds 3.3 V, and (2) the write-only R/W-grounded choice that removes any 5 V return path at the cost of busy-flag polling. On the bench, contrast-first is the rule that saves the most time — a blank-but-backlit display is almost always VO, not a fault.