Circuit review & bench-test guide

AXO-004 — MAX7219 8×8 LED matrix PMOD module

Design-stage — board not yet fabricated

Document purpose#

Component-level explanation and bench-test plan for axo-004-matrix, from generate_design.py, the module README.md, and the MAX7219 and SN74AHCT125 datasheets. Never fabricated; values are verification targets. This board runs the MAX7219 from an external 5 V rail and level-shifts the SPI lines — a mixed-voltage board, so read the sequencing notes.

1. What the board does#

Drives a common 8×8 LED matrix through a MAX7219 display driver over SPI. The MAX7219 is a 5 V part; its 3.3 V logic threshold (VIH ≈ 3.5 V at 5 V supply) is above the FPGA's 3.3 V output, so DIN/CLK/LOAD are level-shifted 3.3→5 V by a 74AHCT125.

PMOD J1  MOSI/SCK/CS ─> U2 74AHCT125 (3.3->5V, VCC=5V) ─> U1 MAX7219 DIN/CLK/LOAD
EXT 5V J3 ─> U1 V+, U2 VCC ; U1 ISET (R1) sets segment current
U1 SEG/DIG ─> J4/J5 matrix socket

2. Safety and scope boundaries#

Two rails: PMOD 3.3 V (logic) and external 5 V (J3, matrix + driver). Bring up 3.3 V first, then 5 V; never leave 5 V applied with the host unpowered if the level-shifter inputs would float (AHCT inputs must not float — see U2 note).
Standalone: 3.3 V into 3V3/GND and 5 V into J3 from a current-limited supply (set ~500 mA; a fully lit matrix at 20 mA/seg is bounded by ISET, not 8×8×20 mA).
Unreleased prototype.

4. Interfaces#

J1 PMOD Type 2 SPI: 1 ~CS(LOAD), 2 MOSI(DIN), 4 SCK(CLK), 3 NC (MAX7219 has no MISO — the display is write-only). 5/11 GND, 6/12 3V3.
J3 external 5 V + GND screw/pin terminal.
J4/J5 matrix socket (2×8 rows for the common 1088AS pinout — verify per Section 4a).

4a. PLUG-IN VERIFICATION#

8×8 matrices come as 1088AS (common-cathode-row) and 788BS (transposed) with differing pinouts. The MAX7219 SEG/DIG mapping assumes one. Before power: buzz the matrix package against J4/J5, confirm which pins are the driver's DIG (digit/row cathodes) vs SEG (segment anodes); if it's the transposed part the image is rotated/mirrored — remap in firmware, don't force it.

5. Component-by-component review#

U1 MAX7219 (SOIC-24W): the display driver — serial in, 8-digit × 8-segment multiplexed constant-current drive. If absent/dead: no matrix output. Runs at 5 V; its DIN/CLK/LOAD VIH ≈ 3.5 V demands the shifter.
U2 74AHCT125 (SOIC-14, quad buffer): the 3.3→5 V level shifter. AHCT has TTL input thresholds (VIH ≈ 2 V) so it accepts 3.3 V, and its VCC=5 V output swings to 5 V for the MAX7219. Three gates used (DIN/CLK/LOAD), one spare. If absent (signals driven directly): the MAX7219 may not see valid highs → intermittent or dead. If a spare gate's input floats: excess supply current and noise — the spare input should be tied.
R1 ISET (28 kΩ): sets peak segment current per the MAX7219 RSET table (~20 mA at VLED ≈ 2 V). If absent/open: no segment current (blank). Too small: over-current, LED/driver stress.
C1/C2/C3 (100 nF + bulk): decoupling for the driver's multiplexed current pulses. If bulk absent: visible flicker/brownout as digits switch.

6. Datasheet summary (MAX7219)#

V+ 4.0–5.5 V; serial 10 MHz max. 16-bit packets: 8-bit register address + 8-bit data, latched on LOAD rising edge. No read-back.
Registers: Decode Mode 0x09, Intensity 0x0A, Scan Limit 0x0B, Shutdown 0x0C (0x01=on), Display Test 0x0F, digits 0x01–0x08.
ISET: RSET from V+ to ISET sets Iseg ≈ 100 × (per the datasheet table); 28 kΩ ≈ 20 mA at VLED 2.0 V.
Boot state = shutdown; must write Shutdown=0x01 before anything appears.

74AHCT125: VCC 4.5–5.5 V, TTL inputs (VIH 2 V), so 3.3 V drives it cleanly.

7. Expected values before bench testing#

After Shutdown=on, ScanLimit=7, Intensity mid, DisplayTest=on: entire matrix lit, current bounded by R1.
U2 outputs swing 0→5 V; U2 inputs see the 3.3 V host levels.

8. Manual review checklist#

[ ] U2 between host and U1 on all three control lines; U2 VCC = 5 V.
[ ] Spare U2 gate input tied (not floating).
[ ] R1 = 28 k from V+ to ISET.
[ ] Matrix orientation identified (Section 4a).
[ ] Bulk decoupling on the 5 V rail.

9. Ordered bench-test procedure#

A. Unpowered: buzz level-shifter path (host→U2→U1), R1 value, matrix pinout; confirm 3V3 and 5V rails are separate and unshorted.

B. Rail sequence: apply 3.3 V first (U2 inputs now defined), then 5 V into J3 (≤500 mA). Confirm U2 outputs idle correctly.

C. Level-shift scope: scope a U2 input (3.3 V) and its output (5 V) while the host toggles CLK; confirm clean 0–5 V output edges.

D. Driver bring-up: send Shutdown=0x01, then Display Test=0x01 → whole matrix lights. Read supply current; confirm bounded by ISET.

E. Pattern: Display Test off; ScanLimit=7, Decode=0x00 (no BCD), write rows 0x01..0x08 with a known bitmap; confirm the image and orientation (remap if 788BS).

F. Intensity sweep: write Intensity 0x00→0x0F; confirm PWM brightness steps.

10. Troubleshooting map#

Blank despite writes: still in shutdown (0x0C), or ISET open.
Dim/wrong highs: level shifter missing or VCC not 5 V (VIH not met).
Rotated image: transposed matrix variant (firmware remap).
Flicker: 5 V bulk decoupling or supply current limit too low.

11. Bench record template#

Board: axo-004  Matrix P/N:____  Orientation identified: [ ]
U2 output swing: __ V   Display-test full-lit current: ____ mA
Pattern correct: [ ]   Intensity steps OK: [ ]
Notes:

12. Review conclusion#

The design's real content is the mixed-voltage handling: an AHCT shifter is mandatory because the MAX7219's 5 V VIH exceeds a 3.3 V drive. Verify the shifter swing and the rail sequence first; everything after is MAX7219 register bring-up. Confirm the matrix variant before trusting the image.