Circuit review & bench-test guide

AXO-003 — Shift-register lab PMOD module

Design-stage — board not yet fabricated

Document purpose#

Component-level explanation and bench-test plan for axo-003-shift-lab, from generate_design.py, the module README.md, and the 74HC595 and KCSC02-105 datasheets. Never fabricated; values are verification targets.

1. What the board does#

Teaches what SPI is by making the student bit-bang a shift chain first: two cascaded 74HC595 serial-in/parallel-out registers. The first drives a single-digit 7-segment display; the second drives 8 LEDs. Data shifted into U1 overflows via QH' into U2 — the cascade is the lesson.

PMOD J1  SER ─> U1 SER ; U1 QH' ─> U2 SER (cascade)
         SRCLK ─> both SRCLK ; RCLK ─> both RCLK (latch) ; ~SRCLR ─> both
         U1 QA..QH ─> 220R ─> 7-seg (U3 KCSC02-105)
         U2 QA..QH ─> 330R ─> 8 LEDs

2. Safety and scope boundaries#

3.3 V only. PMOD host supplies the rail; standalone, 3.3 V current-limited into 3V3/GND (~50 mA covers all segments + LEDs lit).
No hazards beyond LED over-current if a ballast resistor is wrong.
Unreleased prototype.

4. Interfaces#

J1 PMOD Type 1: 1 SER, 2 SRCLK, 3 RCLK, 4 ~SRCLR, 5/11 GND, 6/12 3V3. All four control lines are host-driven (no series R needed).

5. Component-by-component review#

U1, U2 74HC595 (SOIC-16): 8-bit shift + storage register. SER in, SRCLK shifts, RCLK latches to outputs, ~SRCLR clears, ~OE enables (tied low here). QH' is the serial overflow that feeds the next stage. If U1 QH'→U2 SER is open: the second stage never receives data (LEDs dead, 7-seg works). If ~OE floats high: outputs stay hi-Z (nothing lights).
U3 KCSC02-105 (single-digit 7-seg, common-cathode): the display. Segments driven by U1 outputs through 220 Ω. If common cathode isn't grounded: no segments.
R17 (and the segment/LED ballasts): 220 Ω for segments, 330 Ω for LEDs. If absent: over-current on the driver pin and LED.
~SRCLR pull-up (10 k): keeps the registers out of clear when the host pin is unconfigured. If tied low/floating low: registers continuously cleared, nothing latches.
C1, C2 100 nF: decoupling for U1/U2. If absent: switching noise on long shift bursts can corrupt latching.

6. Datasheet summary (74HC595)#

VCC 2–6 V; at 3.3 V, max clock ~30 MHz (far beyond a bit-bang demo).
Two clocks: SRCLK (shift, rising edge) and RCLK (storage latch, rising edge) — the classic "shift all 16 bits, then pulse RCLK once" pattern. Because RCLK is separate, outputs don't glitch during shifting.
~SRCLR async-clears the shift register; ~OE tristates outputs.
Per-pin ±35 mA abs max; keep segment/LED currents well under.

KCSC02-105: 0.28" single digit, common-cathode, Vf ~1.9 V — 220 Ω gives ~6 mA/segment at 3.3 V.

7. Expected values before bench testing#

Idle (after ~SRCLR pulse + RCLK): all outputs low, display blank, LEDs off.
Shift 0xFF into U2's stage, pulse RCLK: 8 LEDs on (~5 mA each).
Shift a segment pattern for "8." into U1's stage: all segments + DP lit.

8. Manual review checklist#

[ ] U1 QH' → U2 SER continuity (the cascade).
[ ] ~OE of both parts tied low; ~SRCLR pulled high.
[ ] Segment ballasts 220 Ω, LED ballasts 330 Ω; U3 common cathode to GND.
[ ] C1/C2 present.

9. Ordered bench-test procedure#

A. Unpowered: verify QH'→SER cascade, ~OE low, ~SRCLR high, common-cathode to GND, no VCC-GND short.

B. Power, idle: 3.3 V. Pulse ~SRCLR low→high then RCLK; confirm blank display, LEDs off, low idle current.

C. Single-stage shift: clock 8 bits (0x01) into SER with SRCLK, pulse RCLK; confirm one U1 output (one segment) lights. Walk the bit to verify each segment maps as expected.

D. Cascade shift: clock 16 bits so the low 8 land in U2; pulse RCLK; confirm the LED byte appears while the 7-seg shows the high byte — proving QH' overflow.

E. Latch timing scope: scope SER, SRCLK, RCLK together; confirm outputs change only on RCLK, not during SRCLK bursts (the glitch-free-latch lesson).

F. Digit sweep: display 0–9 by writing segment patterns; confirm the segment map and DP.

10. Troubleshooting map#

LEDs dead, 7-seg works: broken QH'→SER cascade or U2 ~OE high.
Nothing latches: ~SRCLR held low, or RCLK never pulsed.
Garbled digit: segment-to-output mapping in firmware, not a board fault.

11. Bench record template#

Board: axo-003  Cascade verified: [ ]
Idle blank: [ ]   Single-segment walk OK: [ ]
Cascade (16-bit) OK: [ ]   RCLK-only latching confirmed: [ ]
Digit 0-9 map correct: [ ]
Notes:

12. Review conclusion#

A zero-hazard teaching board; the one thing to verify is the QH'→SER cascade and the RCLK-vs-SRCLK latch behavior on a scope, since that waveform is the lesson that makes the later hardware-SPI modules click.