← AXO-002

Circuit review & bench-test guide

AXO-002 — 4-digit 7-segment direct-scan dual-PMOD module

Document purpose#

This document explains the axo-002-7seg module at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on generate_design.py, README.md, and the schematic/ERC artifacts in this directory.

This board has never been fabricated or assembled. The schematic is reported ERC clean (0/0) and the netlist has been reviewed, but PCB layout has not started, no physical board exists, and there is no first-article bench result of any kind. Every number in this guide is a design target or a datasheet expectation to verify, not a proven result.

1. What the board does#

AXO-002 is a 4-digit common-anode 7-segment display driven by direct scan from the FPGA fabric — there is no controller chip on purpose. It spans two adjacent host PMOD sockets (like the camera module axs-050): J1 carries the 8 segment cathodes (SEG_A…G, DP) and J3 carries the 4 digit enables (DIG1…4).

Because the display is common anode, everything is active-low:

• A segment lights when the FPGA pulls its cathode low through a 220 Ω ballast, sinking the segment current into the host pin.
• A digit lights while its P-channel high-side FET connects the digit's common anode to 3V3, which happens when the host drives that digit's gate low.

The host multiplexes: drive one DIGn low, present that digit's segment pattern on SEG_* (low = lit), rotate through the four digits at ~1 kHz refresh (~250 µs per digit). Per-digit on-time is brightness — that is the PWM-dimming lesson. Persistence of vision, refresh timing, and ghosting are all directly observable; that is the curriculum, not a nuisance. It is a 3.3 V-only module.

Functional block diagram#

J3 (PMOD B: digit enables, active-low)          3V3
  1 DIG1 ─R9 1k─┬─ gate Q1 (AO3401A P-FET) ──────┤ source
  2 DIG2 ─R10 1k┤   R13 10k gate→3V3 (off default)│
  3 DIG3 ─R11 1k┤   drain → DIG1_A common anode   │
  4 DIG4 ─R12 1k┘   ... Q2/Q3/Q4 identical        │
                                                   │
   digit common anodes ──> U1 CA56-12SEKWA <── shared segment cathodes
                          (4-digit common anode)        │
J1 (PMOD A: segment cathodes, active-low)               │
  1 SEG_A ─R1 220R── SEG_A_K ───────────────────────────┤
  2 SEG_B ─R2 220R── SEG_B_K                             │  (FPGA sinks each
  ...                                                    │   segment LOW to light)
 10 SEG_DP─R8 220R── SEG_DP_K ──────────────────────────┘
  C1 100nF at the digit switches;  5/11 GND, 6/12 3V3 on both plugs

2. Safety and scope boundaries#

• Low voltage (3.3 V), low current (a few mA per segment). Hazards are to the board. Standard ESD handling applies; the PMOD signal pins connect straight to the ballast resistors and FET gates.
• 3.3 V only. The AO3401A gate is driven by 3.3 V logic (VGS ≈ −3.3 V when on); a 5 V host would over-drive the gate relative to a 3.3 V source and change the current math.
• This module needs both adjacent PMOD sockets and they must be the correct two. Mis-seating J3 one position over feeds digit-enable logic into a segment bank (or vice versa) — confirm the physical adjacency and pin-1 of both plugs before power.
• Never feed 5 V into any PMOD pin.
• A lit digit is not proof the scan is correct; a static (non-multiplexed) drive that turns on one digit continuously runs each lit segment at full DC, ~4× the intended average — do not leave a single digit statically enabled at high segment count for long during bring-up.

3. Power and signal sequence#

1. The host applies 3.3 V to pins 6/12 and GND to 5/11 on both plugs; C1 (100 nF) charges. No inrush concern.
2. R13–R16 (10 kΩ, gate → 3V3 = FET source) hold every P-FET gate at its source, so all four digits are off by default. An unconfigured FPGA therefore shows a blank display, not garbage — this is the reason the pull-ups exist.
3. To light digit n: the host drives DIGn (J3 pin n) low. The gate is pulled toward 0 V through R(9+n−1) = 1 kΩ; VGS ≈ −3.3 V turns Qn on and connects that digit's common anode to 3V3.
4. Simultaneously the host drives the wanted segment cathodes low on J1 through the 220 Ω ballasts; those segments light. Segments left high stay dark.
5. After ~250 µs the host turns digit n off (DIGn high → gate returns to 3V3 via the 10 k → FET off) and moves to digit n+1. Repeating at ~1 kHz makes all four digits appear steady to the eye.

4. Interfaces#

All lines are active-low. Buzz the 2×6 header zigzag mapping (PMOD pin ↔ header pad) on both plugs before power. There are no test points; probe J1/J3 pins, the FET pads, and the display pins directly.

5. Component-by-component review#

Every reference designator is covered: U1, J1, J3, Q1–Q4, R1–R8 (segment ballast), R9–R12 (gate series), R13–R16 (gate pull-up), C1.

5.1 Display and connectors#

CA56-12SEKWA datasheet note: the cached copy is a 404 page, so the electrical figures below are Kingbright-CA56-series typicals (orange SEKWA die) to confirm against the real sheet before procurement: segment VF ≈ 2.1 V typ at 20 mA, DC IF ≈ 20 mA/segment continuous max, peak IF higher at low duty, reverse voltage ~5 V, λdom ~605 nm.

5.2 Digit high-side switches (P-FET, active-low enable)#

5.3 Segment ballast, gate network, decoupling#

6. Datasheet summary and design interpretation#

Primary references: the CA56 series (Kingbright, confirm exact sheet) for the display and Alpha & Omega AO3401A for the digit FETs.

Segment current math#

Common anode, so the path is 3V3 → Q(digit) RDS(on) → common anode → segment LED → cathode → 220 Ω → host pin (sinking low):

I_seg = (3.3 − Vf_seg − I_seg·RDS_on) / 220
      ≈ (3.3 − 2.1 − ~0.005·0.07) / 220
      ≈ 1.2 / 220 ≈ 5.5 mA per segment

The README's "~10 mA/segment" is a conservative peak assumption (lower Vf, neglecting RDS drop); the realistic average is ~5–6 mA. Either way it is well under the ~20 mA DC segment rating, and because each digit is on ~1/4 of the time the time-averaged segment current is ~1.4 mA — the display looks dimmer than a statically driven one at the same peak, which is exactly why per-digit on-time (duty) is the brightness/dimming control.

Digit FET current and gate drive#

Worst case is all 8 segments lit on one digit: 8 × ~5.5 mA ≈ 44 mA through that digit's AO3401A — trivial for a −4 A part. The subtle point is the gate drive: the host is 3.3 V logic, the FET source is 3V3, so the applied VGS when on is only ≈ −3.3 V, not the −4.5 V at which the datasheet quotes RDS(on). At −3.3 V the AO3401A is fully enhanced (threshold ~−1.3 V) but its RDS(on) is somewhat higher than the datasheet number — measure the actual anode drop rather than extrapolate. The 10 kΩ pull-up guarantees VGS = 0 (off) whenever the host pin is high or tri-stated.

Why the display is blank at power-up (a feature)#

All four gate pull-ups tie to 3V3 = FET source, so with no host drive every digit is off and no segment can source current. An unconfigured FPGA shows a dark display instead of random glyphs — the intended, safe default.

7. Expected values before bench testing#

None have ever been measured — no board exists.

8. Manual schematic and assembly review checklist#

• Confirm U1 is common anode (CA56, not a CC part) and its pin map matches SEGMENT_PINS/DIGIT_PINS in generate_design.py; a rotated display scrambles both.
• Verify each AO3401A: source→3V3, drain→the correct DIGn_A common anode, gate→its 1 k (from DIGn) and 10 k (to 3V3). A source/drain swap defeats the high-side switch.
• Confirm all four 10 kΩ gate pull-ups go to 3V3 (the FET source), not GND — a pull-up to GND would turn every digit permanently on.
• Confirm R1–R8 = 220 Ω, R9–R12 = 1 kΩ, R13–R16 = 10 kΩ; a 220/1k/10k mix-up is easy on an all-0603 board.
• Verify J1 and J3 pin-1 against the Digilent PMOD spec and a real host, and that the two plugs' spacing matches the host PMOD pitch (same dual-plug constraint as axs-050). Buzz both zigzag maps.
• Confirm C1 sits at the digit switches.
• Silkscreen: segment/digit legend and the "needs both PMODs" note.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host/supply, equipment, ambient, and operator. Contexts: standalone (bench supply + manual/logic drive, phases A–C) then PMOD host (FPGA scan, phase D). Do standalone first.

A. Unpowered inspection and resistance tests#

1. Complete the section 8 checklist under magnification.
2. DMM each DIGn (J3) to 3V3: ~10 kΩ (through the gate network). To GND: open.
3. DMM each SEGn (J1) to a digit anode pin: 220 Ω + diode. 3V3 to GND: high.

B. Standalone digit-switch bring-up (current-limited supply)#

1. Supply 3.3 V, limit ~200 mA, on both plugs' 3V3/GND. Output on: expect µA idle (all digits off — confirm blank display, proving the pull-ups work).
2. Manually pull one DIGn low (short J3 pin to GND through a 1 k lead is not needed — the on-board 1 k is in series; tie the pin to GND). Measure the FET gate ≈ 0 V, VGS ≈ −3.3 V, and the digit's common anode rise to ~3.2 V. Digit-driver check: confirm exactly that one digit's anode energizes.
3. With that digit enabled, pull one SEGn low (to GND): that single segment on that single digit lights at ~5–6 mA. Measure the segment current.
4. Release; the segment and digit must extinguish (no stuck-on = pull-ups and gate network intact).

C. Static illumination and current check#

1. Enable one digit, pull all 8 SEG lines low: the whole "8." lights. Measure the digit-FET current ≈ 44 mA. Do not hold this DC state long (4× the intended average per segment).
2. Measure the anode drop (3.3 − Vanode) to back out the AO3401A RDS(on) at the real −3.3 V gate drive; compare to the datasheet −4.5 V number.

D. PMOD-host context (FPGA direct scan)#

1. Verify both host sockets supply 3.3 V and are the correct adjacent pair. Plug in J1 and J3. Confirm a blank display before the scan core runs.
2. Run the seg7_scan core at ~1 kHz. Scan-rate scope capture: probe one digit anode; confirm ~250 µs on-time, ~25% duty, ~1 kHz period, and that the four digit anodes are non-overlapping (only one high at a time). Overlap = two digits on together = cross-illumination.
3. Ghosting test: display a pattern where adjacent digits differ (e.g. "1 8"), then deliberately raise the scan rate or shorten the inter-digit blanking. Watch for faint segments bleeding onto the neighbor digit — ghosting from a digit anode not fully discharged before the next digit's segments are asserted. Confirm the intended blanking interval removes it. This is a teaching capture, not necessarily a defect.
4. Dimming: sweep per-digit on-time (duty) and confirm smooth brightness control with no flicker at the chosen refresh; drop the refresh until flicker appears to find the persistence-of-vision threshold (the lesson).
5. Counter/clock demo: run a counting value across all four digits; confirm correct glyphs and digit order (a wrong order is a J3 pin-map or scan-order error).

E. Release-only tests#

Long-duration thermal behavior at high brightness, segment-current derating, apparent-brightness uniformity across digits, ESD, and the dual-plug mechanical fit against production hosts are out of scope for the first bench pass.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The circuit is a clean direct-scan common-anode display: eight 220 Ω segment ballasts, four AO3401A high-side digit switches with 1 kΩ gate series and 10 kΩ pull-ups, and one decoupling cap — with all display work left to the FPGA on purpose. The active-low logic falls straight out of the common-anode topology (pull a cathode low to light a segment, pull a gate low to enable a digit), and the gate pull-ups give the important safe default of a blank display on an unconfigured host. The principal risks are unverified first-article behavior, the CA-vs-CC and rotation orientation of the display, the AO3401A RDS(on) at the reduced −3.3 V gate drive (measure, don't extrapolate), scan overlap/ghosting that must be tuned in HDL and captured on a scope, and the dual-PMOD adjacency and pin-1 alignment against a real host. The scan sequence in section 9 — one digit low, its segment pattern low, rotate at ~1 kHz — is exactly what the seg7_scan core must reproduce.