← AXL-008

Circuit review & bench-test guide

AXL-008 — Breadboard adapter PMOD module

Document purpose#

This document explains the axl-008-breadboard prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic, 2026-07-12), the README, and the Digilent Pmod Interface Specification 1.2.0.

The board is a design-stage prototype. The schematic is generated and the ERC report in reports/erc.rpt (2026-07-12) shows 0 errors / 0 warnings (with the tool's standard ignored-check list), but note that the schematic file carries a later modification timestamp than that report — ERC must be re-run before release. PCB layout has not started and no board has been fabricated or assembled. There is no first-article bench result of any kind. Every expected value below is a design target to verify, not proof that an assembled board works. The board has no ICs; its entire correctness budget is spent on the netlist, the resistor values, and — once layout exists — the silkscreen labels that this guide treats as part of the design.

1. What the board does#

The board is a 12-pin PMOD (Type 1A expanded-GPIO footprint) to breadboard adapter: PMOD plug J1 passes all 12 positions to two labeled 1x06 pin-header rows (J2, J3) intended to straddle a solderless breadboard at 0.3" DIP row spacing. The 8 signal lines each pass a 100 Ω series resistor (survivability: a breadboard miswire burns nothing); GND and 3V3 pass straight through. Net B<n> corresponds to PMOD signal pin n, and the silkscreen label next to each breakout pin is intended to be exactly the net name, so the breadboard rows read like the PMOD specification: row A = B1 B2 B3 B4 GND 3V3, row B = B7 B8 B9 B10 GND 3V3.

It is the classroom adapter of the AruviX lab line (catalog #8, level L1); there is no active silicon, no decoupling (nothing to decouple), and no protection beyond the eight series resistors.

Functional block diagram#

PMOD J1                        J2 ROW A (breadboard)
 1 P1 ── R1 100R ── B1 ─────── 1 B1
 2 P2 ── R2 100R ── B2 ─────── 2 B2
 3 P3 ── R3 100R ── B3 ─────── 3 B3
 4 P4 ── R4 100R ── B4 ─────── 4 B4
 5 GND ─────────────────┬───── 5 GND
 6 3V3 ─────────────────┼┬──── 6 3V3
                        ││     J3 ROW B (breadboard)
 7 P7 ── R5 100R ── B7 ─┼┼──── 1 B7
 8 P8 ── R6 100R ── B8 ─┼┼──── 2 B8
 9 P9 ── R7 100R ── B9 ─┼┼──── 3 B9
10 P10 ─ R8 100R ── B10 ┼┼──── 4 B10
11 GND ─────────────────┘│──── 5 GND
12 3V3 ──────────────────┘──── 6 3V3

2. Safety and scope boundaries#

• Solderless breadboards and long jumper wires are poor high-speed and high-current interconnects. Contact resistance is tens of milliohms to ohms and degrades with use; row capacitance (~2–25 pF) plus the 100 Ω series resistors and jumper inductance limit clean edges to the low-MHz region. The PMOD spec itself calls the interface "low frequency". Do not route clocks faster than a few MHz, DDR strobes, or anything whose timing you care about through this adapter, and never carry more than ~0.5 A through a single breadboard contact.
• 3V3 pin current limits. The Pmod specification says a module "should not be assumed" to draw more than approximately 100 mA from the host's power pins, and the actual limit is set by the host's 3.3 V regulator and any per-port fuse/switch (ULX3S-class boards share one rail across ports). Treat 100 mA as the budget for everything on the breadboard; power hungry circuits get their own supply, joined to the adapter only at GND.
• What must never be jumpered together: 3V3 to GND (nothing on this board limits that current — it is a dead short across the host rail); 3V3 to any B pin while the host drives that pin low (33 mA continuous through one 100 Ω resistor, ~109 mW — above the 0603's rating, see Section 5); any external supply above 3.3 V (5 V included) to 3V3 or to any B pin — the ECP5's I/O are not 5 V tolerant and 100 Ω is a survivability resistor, not level translation; and two B pins both configured as driven outputs (16.5 mA contention — survivable through 2 x 100 Ω but always a design error to fix).
• The spec allows hosts to offer switchable 5.0 V on the power pins. This adapter must only be used on hosts set to 3.3 V; at 5 V every label on the board ("3V3") becomes a lie and downstream 3.3 V breadboard parts are at risk.
• Earth-referenced oscilloscope grounds clip only to a GND pin.
• A passing continuity test is not a signal-integrity qualification; this adapter is verified for DC correctness only.

3. Power and control sequence#

There is none, honestly: the board is entirely passive. 3V3 and GND arrive on PMOD pins 6/12 and 5/11 and appear immediately and unconditionally on J2/J3 pins 5 and 6. The eight signals are live whenever the host drives them; the board adds nothing but 100 Ω per line. There is no inrush behavior worth noting (no capacitors), no reset, and no configuration. The only sequencing rule is imported from the host: configure the FPGA pins as inputs (or keep the FPGA unconfigured) while wiring the breadboard, and drive outputs only after the wiring is inspected.

4. Interfaces and pin maps#

Full PMOD-pin to labeled-breakout-pin map (the authoritative netlist, from generate_design.py):

Note the deliberate naming gap: there are no B5/B6/B11/B12 — the B numbers track PMOD signal pin numbers, and pins 5/6/11/12 are GND/3V3. The two GND nets are one net; the two 3V3 nets are one net.

Label-vs-net verification (design review, pre-fabrication): silkscreen does not exist yet — layout has not started. When it does, a mandatory review step is to cross-check every label string placed on the silkscreen against the net name attached to that pad in generate_design.py (the script's own comment says the labels are the net names — hold layout to that). The corresponding bench step is Section 9.C: drive one pin from the host and confirm only the identically labeled breakout pin toggles.

Orientation caution: the spec's 2x6 pin numbering is "non-standard and mirrored between the host connector and the peripheral board connector" (spec Section 4, Figures 2 and 5). The layout review must confirm J1 pin 1 lands on host pin 1 with the module plugged in the intended orientation; this is the single most likely way for every label on the board to be wrong at once.

5. Component-by-component review#

Every reference designator in generate_design.py appears below. There are no DNP parts on this design. #FLG01 and #FLG02 are ERC power-flag pseudo-components on 3V3 and GND; they have no physical footprint and are listed only for completeness.

Protection-current math the 100 Ω choice implies: worst continuous fault is one line hard-shorted to the opposite rail while driven, giving 3.3 V / 100 Ω = 33 mA through the resistor and 3.3 V² / 100 Ω = 109 mW dissipation — about 9% above the RC0603FR's 100 mW rating at 70 °C. That is fine for the intended "miswire, notice, fix" transient, but a fault left in place indefinitely runs the resistor out of spec (an open risk carried to Section 12; an 0805 would add margin at layout time). Contention between two driven pins splits 3.3 V across 200 Ω: 16.5 mA, 27 mW per resistor — comfortably safe. The 33 mA fault figure is also inside what ECP5 LVCMOS33 outputs survive briefly, which is the point of the resistor.

6. Specification summary and design interpretation#

There is no silicon on this board, so there is no device datasheet to review — deliberately. The governing document is the Digilent Pmod Interface Specification 1.2.0 (revised October 5, 2017), <https://digilent.com/reference/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf> (fetched and read in full for this review), plus the Yageo RC-series thick film resistor datasheet for R1–R8.

Check the current specification revision before layout; 1.2.0 is the latest known at review time.

7. Expected values before bench testing#

All are design targets derived from the netlist and the 1% resistor tolerance, not measured results. "Unplugged" means the bare adapter, out of the host and off the breadboard — the only configuration in which the resistors read true, because the board itself has no parallel paths but a host or a populated breadboard adds them (FPGA clamp diodes, host series resistors, whatever is wired on the breadboard).

8. Manual schematic and assembly review checklist#

• Re-run ERC after any regeneration: the checked-in reports/erc.rpt (0 errors / 0 warnings) predates the current schematic file timestamp.
• Verify all eight nets: Bn connects to PMOD pin n through exactly one resistor, and to nothing else. Confirm there are no B5/B6/B11/B12 nets.
• Confirm GND ties pins J1-5, J1-11, J2-5, J3-5 and 3V3 ties J1-6, J1-12, J2-6, J3-6, with no series parts.
• Confirm R1–R8 are all 100 Ω 1% (RC0603FR-07100RL) and each sits between the correct P/B pair per the Section 5 table.
• At layout review (not yet possible): cross-check every silkscreen label string against the pad's net name in the netlist (Section 4); confirm J1 orientation against Pmod spec Figure 2 with the mirrored host numbering in mind; confirm J2/J3 land at 0.3" row-to-row spacing and the board meets the 0.8" width / 25 mil clip-clearance rules; consider 0805 resistors for fault-dissipation margin.
• Resolve the pin-header MPN (currently "TBD" in the script and README) and run the BOM availability check before release.
• On an assembled board: inspect for solder bridges between the 100 mil header pins and between adjacent 0603 pads; verify no resistor position swaps matter (they are identical values — a swap is benign, a bridge is not).

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host identity, DMM model, and measured host 3V3. Two bench contexts are used: (a) the module on an ECP5/ULX3S-class FPGA PMOD host driving known patterns into a breadboard, and (b) the bare module standalone with a DMM. Do all of context (b) before ever plugging into a host.

A. Standalone continuity matrix and resistance tests (unplugged, DMM)#

1. Complete the assembly checklist above under magnification.
2. Measure 3V3-to-GND in both polarities: expect open.
3. Buzz every PMOD pin to its labeled breakout pin. Use ohms mode, not the continuity beeper, for the signal rows — many beepers threshold near 30–50 Ω and will stay silent through a healthy 100 Ω resistor. Fill in:

The 99–101 Ω readings are simultaneously the series-R value check: each in-circuit reading here equals the true resistor value because the bare board has no parallel path across any resistor. If a reading is low, suspect a solder bridge across the 0603; if high/open, a cracked joint or wrong part. Verify the value and 1% tolerance against the BOM line (RC0603FR-07100RL). Once the module is plugged into a host or breadboard this measurement is no longer trustworthy — host clamp diodes, host series resistors, and breadboard wiring all appear in parallel or series.

1. Adjacent-pair short scan across the whole J1 header — every physically adjacent pair, along each row and across the rows. Expected: open everywhere except the two power pairs marked, which are single nets.

1. Repeat the same adjacent-pair scan across J2's six pins and J3's six pins (all open except nothing — J2/J3 adjacent pins share no nets; GND and 3V3 are adjacent on each row, expected open to each other).

B. First power on the FPGA host, no signal traffic#

1. Plug the module into a 3.3 V PMOD port on the ECP5 host (ULX3S-class) with the FPGA unconfigured (all I/O high-impedance). No breadboard yet.
2. Confirm the host powers up normally and its 3V3 rail current is unchanged (the adapter draws nothing).
3. Measure J2-6 and J3-6 to J2-5: expect the host's 3V3 rail value (typically 3.25–3.35 V), identical at both pins.
4. Measure each B pin: undriven FPGA pins may float or sit at the host's pull-up/pull-down default; note but do not judge the values.

C. Label verification by walking-one pattern (host drives)#

This is the electrical proof of the silkscreen. Configure the FPGA to drive a walking-one: exactly one of P1–P4/P7–P10 high (or slowly toggling, ~1 Hz) and the other seven driven low.

1. For each of the eight signals in turn, probe all eight B pins with the DMM (or watch eight LEDs, each 3.3 kΩ-ish series, one per breakout pin on the breadboard).
2. Pass criterion: only the breakout pin whose label matches the driven host pin goes high; the other seven stay low. A wrong-but-consistent mapping (e.g. rows swapped, or the whole header mirrored) shows up here as a pattern and means the layout orientation or label placement is wrong — that is a design/layout defect, not a rework item.
3. Record the 8x8 observation as a diagonal matrix in the bench record; any off-diagonal high is a fail.
4. Repeat with the walking bit inverted (walking zero, others high) to catch stuck-high faults the walking-one misses.

D. Loaded-level and loopback checks (host + breadboard)#

1. Load one driven-high B pin with 3.3 kΩ to GND on the breadboard: expect ~3.20 V at the breakout pin (Section 7). Significantly lower suggests extra series resistance (bad header/breadboard contact) — reseat and remeasure before blaming the board.
2. Loopback: jumper B1 to B2 on the breadboard; drive P1 from the host and read P2 as an input. The path is 200 Ω total — logic levels are unaffected at input-leakage currents. Walk the loopback across pairs (B3–B4, B7–B8, B9–B10) to exercise every line in both directions.
3. This loopback plus the walking-one is the full functional coverage of a passive adapter; there is nothing else to test functionally.

E. Optional signal-quality characterization (scope)#

Not a pass/fail gate — a calibration of expectations for the lab line's documentation.

1. Drive a 1 MHz square wave on one line; scope at the breakout pin and at the far end of a typical breadboard run. Record rise time and overshoot.
2. Increase frequency until edges are visibly unusable; record the ceiling. Expect trouble in the low-MHz region (Section 2); publish the measured number in the lab-line docs rather than the estimate.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design does exactly what a trivial board should: one resistor per signal, straight power pass-through, and a naming scheme (Bn = PMOD pin n, labels = net names) that makes the netlist self-documenting and the bench tests almost mechanical. The README and generate_design.py agree with each other on every net, value, and reference designator. The 100 Ω choice is a sound survivability compromise: it caps miswire current at 33 mA while costing only 100 mV per mA of legitimate load.

The open risks are real, though. No PCB layout exists, and for this board the layout is most of the remaining design: silkscreen-label-to-net correctness, connector orientation against the spec's mirrored numbering, and the 0.3" DIP row spacing are all unverified and are the only ways this board can meaningfully fail. The checked-in ERC report predates the current schematic file and must be re-run. The sustained-fault dissipation (~109 mW) slightly exceeds the chosen 0603's 100 mW rating — acceptable for transient miswires, worth revisiting (0805) at layout. The pin-header MPN is still TBD, and every expected value in this guide is calculated from the netlist and the Pmod specification rather than measured on hardware, because no hardware exists.