← AXL-006

Circuit review & bench-test guide

AXL-006 — Grove + Qwiic adapter PMOD module

Document purpose#

This document explains the axl-006-grove-qwiic prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic, 2026-07-12), the README, the SparkFun Qwiic connect standard, and the Seeed Grove system documentation.

The board is a design-stage prototype. The schematic is generated and ERC clean (reports/erc.rpt, 2026-07-12: 0 errors / 0 warnings) and the netlist has been reviewed, but PCB layout has not started and no board has been fabricated or assembled. There is no first-article bench result of any kind. Every expected value below is a design target to verify, not proof that an assembled board works.

Prominent stand-in caveat: the two Grove sockets (J4, J5) use a generic PinHeader_1x04_P2.00mm_Vertical footprint standing in for the real Seeed HY-2.0 4P connector, which is confirmed absent from the stock libraries. The 2.00 mm header is pin-compatible, but the stand-in has no shroud outline and its mechanical footprint and pin-1 orientation must be verified against the real connector before fabrication; mating polarity cannot be verified until the real part is in hand. The MPN field in the schematic is deliberately "TBD".

1. What the board does#

The board is a 12-pin PMOD (Type 6 extended I2C, plus a GPIO pair on pins 7/8) adapter that opens two hobbyist sensor ecosystems to the AruviX lab hosts: 2x Qwiic/STEMMA QT sockets (JST-SH, SparkFun/Adafruit ecosystem) and 2x Grove sockets (Seeed ecosystem). Both Qwiic sockets, Grove socket 1, and the PMOD I2C pins share one I2C bus with a single set of 4.7 kΩ pull-ups (R3/R4) that can be disconnected via solder jumpers JP1/JP2. Grove socket 2 carries two GPIO lines (D0/D1) to PMOD pins 7/8 through 100 Ω series resistors.

There is no major silicon on this board — no level shifter, no buffer, no regulator, no ADC. It is passives, connectors, and copper. Everything a host sees on the bus comes from whatever modules are plugged into the sockets. The board is 3.3 V only; 5 V Grove modules belong on AXL-005.

Functional block diagram#

PMOD J1                         shared I2C bus
 3/9  SCL ──┬── JP2 ── R4 4.7k ── 3V3
 4/10 SDA ──┼── JP1 ── R3 4.7k ── 3V3
            │
            ├── J2 QWIIC 1 (JST-SH): 1 GND, 2 3V3, 3 SDA, 4 SCL
            ├── J3 QWIIC 2 (JST-SH): 1 GND, 2 3V3, 3 SDA, 4 SCL
            └── J4 GROVE 1 I2C (2.0mm stand-in): 1 SCL, 2 SDA, 3 VCC, 4 GND

 7 D0 ── R1 100R ── G_D0 ── J5.1 ┐ GROVE 2 GPIO (2.0mm stand-in)
 8 D1 ── R2 100R ── G_D1 ── J5.2 ┘ 3 VCC, 4 GND

 5/11 GND, 6/12 3V3 ── C1 100n + C2 10u (socket-side rail)

2. Safety and scope boundaries#

• 3.3 V only. Never plug a 5 V-only Grove module into J4/J5 and never feed the board from a 5 V PMOD host. Nothing on this board limits, regulates, or level-shifts; a 5 V module puts 5 V logic straight onto the FPGA pins.
• The whole board plus every plugged module runs from the PMOD 3V3 pins. Budget the host's PMOD supply (design note assumes a ~100 mA class budget); the Qwiic spec allows chains drawing far more than a PMOD port can source — check plugged-module current before chaining.
• The Grove sockets are a stand-in footprint. Until the HY-2.0 part is in hand, treat J4/J5 pin-1 orientation as unverified: a reversed Grove cable puts VCC on SCL and GND on SDA. Buzz the assembled socket against the cable before powering any module.
• Standalone bench work uses a current-limited 3.3 V supply (limit ~100 mA to start; the bare board draws only pull-up and leakage current).
• Earth-referenced oscilloscope grounds clip only to board GND.
• D0/D1 on Grove socket 2 may be driven by either side (that is why R1/R2 exist); never configure both the FPGA and a plugged module as push-pull outputs on the same line for longer than a contention test.
• A successful I2C scan is not a validation of any plugged module; this board only proves wiring and bus levels.

3. Power and control sequence#

1. 3V3 and GND arrive on PMOD pins 6/12 and 5/11. C1 (100 nF) provides high-frequency decoupling at the sockets; C2 (10 µF) is a bulk reservoir for plugged Qwiic/Grove devices within the PMOD current budget.
2. There is no power switching, sequencing, or inrush control: socket VCC pins are hard-wired to the PMOD rail. Plugged modules power up the instant the host rail is up (or the instant they are hot-plugged).
3. R3/R4 (4.7 kΩ) pull SDA/SCL to 3V3 through solder jumpers JP1/JP2 (bridged by default), so the idle bus sits at 3V3.
4. The host (FPGA or lab adapter) is the I2C controller; every plugged module is a target. This board contributes no addresses of its own — an empty board ACKs nothing on a scan.
5. G_D0/G_D1 idle floating unless a plugged Grove module or the host defines them; there are no pull resistors on the GPIO pair, only the 100 Ω series elements R1/R2.

4. Interfaces and pin maps#

Qwiic sockets J2, J3 (JST SM04B-SRSS-TB, stock verified footprint)#

This matches the SparkFun Qwiic connect standard exactly (GND, 3.3 V, SDA, SCL on a JST-SH 1.0 mm 4-pin), as wired in generate_design.py. No deviation.

Grove sockets J4 (I2C) and J5 (GPIO) — 2.00 mm header stand-in#

Both match the Seeed Grove convention (pin 1 = primary signal, pin 2 = secondary signal, pin 3 = VCC, pin 4 = GND) as wired in generate_design.py. No electrical deviation — but the physical connector is the stand-in header, so pin-1 location on the PCB is unverified until the HY-2.0 footprint is checked (Section 8).

How the two standards meet on one bus#

Qwiic and Grove I2C carry the same four nets in opposite order:

Grove I2C order is exactly the Qwiic order reversed (pin 1 ↔ pin 4, pin 2 ↔ pin 3). The adapter resolves this purely in copper: each socket's pins are wired to the correct shared nets, so plugged devices from both ecosystems land on the same SCL/SDA/3V3/GND. This reversal is also why a mis-oriented Grove stand-in footprint would be so damaging — a mirrored socket applies 3V3/GND to SDA/SCL.

5. Component-by-component review#

Every reference designator in generate_design.py appears below. #FLG01 and #FLG02 are ERC power-flag pseudo-components on 3V3 and GND; they have no physical footprint and are listed only for completeness. JP1/JP2 are excluded from BOM and placement (in_bom=False, in_pos=False) because they are copper-and-solder features, not purchased parts.

6. Specification summary and design interpretation#

Consulted: SparkFun Qwiic connect system page, <https://www.sparkfun.com/qwiic> (fetched 2026-07-14), and the Seeed Grove system wiki, <https://wiki.seeedstudio.com/Grove_System/> (fetched 2026-07-14). There is no silicon datasheet to summarize because there is no major silicon on this board — the governing documents are the two ecosystem standards plus the I2C-bus specification's 3 mA / 0.4 V open-drain sink figure.

Check the ecosystem pages and the eventual HY-2.0 socket datasheet again before procurement.

7. Expected values before bench testing#

Targets assume VDD = 3.300 V and an otherwise empty board. All are design targets, not measured results.

8. Manual schematic and assembly review checklist#

• Grove stand-in verification (blocking for fabrication): compare the PinHeader_1x04_P2.00mm_Vertical land pattern against the real Seeed HY-2.0 4P socket drawing — pin pitch, pad size, body outline, and above all which end is pin 1 when the socket's key faces its documented direction. Add the shroud courtyard/silk rectangle manually at layout (README release item) before DRC.
• Confirm J2/J3 (JST-SH) pin 1 marking matches the Qwiic standard: pin 1 = GND at the correct end of the polarized housing.
• Verify JP1/JP2 are bridged for a first build and note their state on the bench record.
• Measure R3/R4 = 4.7 kΩ from SDA/SCL to 3V3, R1/R2 = 100 Ω from PMOD 7/8 to J5 pins 1/2.
• Buzz PMOD pins 3-to-9 (SCL) and 4-to-10 (SDA) — paired nets.
• Buzz every socket pin to its net per the Section 4 tables, including the Qwiic-vs-Grove reversal: J2 pin 1 must be GND while J4 pin 1 must be SCL. This single check catches the worst assembly outcome.
• Check C1/C2 placement near the sockets during layout review (layout not yet started — carry forward).
• Confirm the silkscreen carries the "3.3 V only" warning and each socket's pin-1 marker (carry forward to layout).

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host identity, bus speed, measured 3V3, JP1/JP2 states, and the identity of every plugged module.

A. Unpowered inspection and resistance tests#

1. Complete the checklist above under magnification.
2. Measure 3V3-to-GND resistance in both polarities; investigate < 10 kΩ (after C2's charging transient settles on the meter).
3. Confirm SDA and SCL each read ~4.7 kΩ to 3V3 and are not shorted to each other or to GND.
4. Buzz all four pins of each of J2/J3/J4/J5 to their Section 4 nets. For J4/J5 do this again with the real Grove cable plugged, from the cable's far end, before any module is attached — this is the only defense against the stand-in orientation risk.

B. First power, no modules plugged#

Context (a) — PMOD host: plug into a 3.3 V PMOD port on the ECP5 host (ULX3S-class) with the FPGA unconfigured. Context (b) — standalone: wire 3V3/GND from a current-limited bench supply (limit ~100 mA) and SDA/SCL to a 3.3 V lab adapter (Raspberry Pi Pico, FT2232H, Bus Pirate — I2C mode).

1. Supply current ~0 (µA range); investigate anything above ~1 mA on the bare board.
2. SDA and SCL idle at 3.3 V; J2/J3 pin 2 and J4/J5 pin 3 read 3.3 V; pins 1 (J2/J3) and 4 (J4/J5) read 0 V.
3. Run an I2C scan: the empty board must ACK nothing. Any ACK means a solder bridge or adapter artifact.

C. Single Qwiic device bring-up#

1. Plug one known-good Qwiic module (e.g. any SparkFun sensor with a documented address) into J2. Bus speed 100 kHz.
2. Scan: exactly the module's address(es) must ACK.
3. Read a known register (WHO_AM_I or equivalent) and verify the documented value.
4. Scope SDA and SCL during the read: V_OL ≤ 0.4 V, clean edges. Note the effective pull-up is now ~1.50 kΩ if the module carries the typical 2.2 kΩ (Section 6).
5. Move the module to J3 and repeat — proves both Qwiic sockets.

D. Single Grove I2C device bring-up#

1. Plug one known-good Grove I2C module into J4 only after the cable buzz-out of step A.4 passed on this exact socket.
2. Scan, read a known register, and scope V_OL as in step C.
3. If the module carries 10 kΩ pull-ups (common on Grove designs), the effective pull-up with JP bridged is 4.7k∥10k ≈ 3.2 kΩ — well within spec; record the measured idle-high and low levels anyway.

E. Chained-device test (Qwiic + Grove simultaneously)#

This is the module's reason to exist: both ecosystems on one bus.

1. With power off, plug one real Qwiic device into J2 and one real Grove I2C device (different address) into J4 simultaneously.
2. Power up; supply current must equal roughly the sum of the two modules' datasheet figures.
3. Scan: both addresses must ACK, and nothing else. A missing address means a socket or cable fault; an extra address means an address conflict or bridge.
4. Read a known register from both devices in one session.
5. Scope SDA/SCL: measure idle-high (3.3 V) and V_OL during each device's ACK. Compute the effective pull-up from the parts present (board 4.7 kΩ ∥ each module's pull-ups) and check V_OL is consistent with ≤ 3 mA sink. If a second Qwiic device is added to J3 (three pulled-up nodes), expect the 0.89 kΩ-class stiffness of Section 6 — cut JP1/JP2 and re-measure: idle must stay at 3.3 V (module pull-ups now carry the bus) and V_OL must improve.
6. Run a sustained alternating read loop (a few minutes) at 100 kHz, then repeat at 400 kHz; zero NACK/timeout errors.

F. Grove GPIO socket test#

1. Standalone context: connect the adapter's two spare GPIOs (or the FPGA's PMOD 7/8 in context (a)) and plug a simple Grove digital module (e.g. button or LED module) into J5.
2. Input direction: press/release the button module; the host must see clean 0/3.3 V levels through R1/R2 on D0.
3. Output direction: drive an LED module from the host; verify the level at J5 pin 1/2 is within ~0.1 V of the driven rail (drop across 100 Ω at LED-module currents is small but nonzero — record it).
4. Deliberate contention check (brief): with the host driving low and the line externally tied high through a 1 kΩ test resistor, confirm current is bounded as expected; never hard-short a driven line to a rail.

G. Host-integration regression#

1. In the PMOD-host context, run the eventual HDL I2C controller against the step-E two-device configuration; scans and reads must match the lab adapter's results exactly.
2. Long-cable, EMC, and temperature testing are out of scope for the first article.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The design is an honest, minimal adapter: correct Qwiic order on a verified stock JST-SH footprint, correct Seeed order on the Grove nets, one shared bus with a single cuttable pull-up pair — the right architecture for mixed-ecosystem chaining, since plugged Qwiic modules bring their own pull-ups and the parallel combination gets illegal fast (two 2.2 kΩ modules plus the board's 4.7 kΩ is already past the 3 mA sink limit). The 100 Ω series resistors on the bidirectional Grove GPIO pair and the decoupling pair are appropriate for an L1 classroom module. The principal open risks: the Grove sockets are an unkeyed 2.00 mm header stand-in with no shroud outline, no confirmed MPN, and unverifiable mating polarity until the real HY-2.0 part is procured and the footprint checked against it (the single most likely way this board damages a plugged module); PCB layout has not started, so silkscreen warnings, courtyards, and decoupling placement are all still promises; nothing prevents a 5 V-only or over-budget module from being plugged; and every value in this guide is calculated from the two ecosystem standards rather than measured, because no board exists.