← AXL-005

Circuit review & bench-test guide

AXL-005 — 5 V Arduino-kit module adapter PMOD

Document purpose#

This document explains the axl-005-arduino prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the generated schematic (generate_design.py, rev 0.1-schematic, 2026-07-12), the README, and the TI SN74AHCT1G125 and SN74LVC1G125 datasheets.

The board is a design-stage prototype. The schematic is generated and ERC clean (reports/erc.rpt, 2026-07-12: 0 errors / 0 warnings) and the netlist has been reviewed, but PCB layout has not started and no board has been fabricated or assembled. There is no first-article bench result of any kind. Every expected value below is a design target to verify, not proof that an assembled board works.

1. What the board does#

The board is a 12-pin PMOD (Type 1 GPIO) adapter that makes cheap 5 V Arduino "37-in-1" kit modules usable on a 3.3 V AruviX FPGA host. Four S/V/G sockets (J2–J5) take one kit module each at its native 5 V, powered from an external screw terminal (J6, EXT_5V). Each channel level-shifts one signal between the 5 V socket S pin and a 3.3 V PMOD pin (CH1–CH4).

Per a binding line-README review finding, the auto-direction TXS0108E was rejected (edge-rate sensitive, drives LEDs and long kit wires poorly). Direction is known per socket, so each channel instead uses two fixed-direction single-gate buffers with jumper-selected, complementary enables: a SN74AHCT1G125 (VCC = EXT_5V; TTL-compatible input accepts 3.3 V logic directly) drives the socket in output mode, and a SN74LVC1G125 (VCC = 3V3; input is 5 V-tolerant) receives from the socket in input mode, through a 100 Ω series resistor to the PMOD. A 3-pad solder jumper per channel (common pad = GND) grounds exactly one gate's active-low OE; the other OE is pulled to its own rail by a dedicated 10 kΩ, so at most one gate is ever enabled. A 100 kΩ pull-down defines each S pin with no module fitted.

Functional block diagram#

PMOD J1 (Type 1)                per channel n = 1..4              socket J(n+1)
 1..4 CHn ──┬──────────────────> A  Un AHCT1G125  Y ──┬─────────── 1 S (Sn)
            │                       VCC=EXT_5V ~OE=DIRn_TX         2 V (EXT_5V)
            │                          ▲ R(n+4) 10k to EXT_5V     3 G (GND)
            │                          └ JPn pad 3                 │
            └── Rn 100R ── CHn_RX <─ Y  U(n+4) LVC1G125 A <────────┤
                                        VCC=3V3 ~OE=DIRn_RX        │
                                           ▲ R(n+8) 10k to 3V3     R(n+12) 100k
                                           └ JPn pad 1             to GND
 JPn: pad 2 = GND (common); bridged 1-2 (default) = input mode,
      bridged 2-3 = output mode, open = both Hi-Z
 5/11 GND, 6/12 3V3 ── C(n+4) 100n, C10 10u    J6: 1 EXT_5V, 2 GND
 EXT_5V ── C(n) 100n per AHCT, C9 10u bulk     pins 7-10 NC

2. Safety and scope boundaries#

• EXT_5V comes from the external screw terminal J6 only. It is never routed to the PMOD 3V3 pins, and nothing on the board regulates, reverse-protects, or fuses it. Wire J6 carefully: reversed polarity or a rail above 5.5 V goes straight to four AHCT gates and every plugged kit module. Use a current-limited bench supply (≤ 500 mA is ample).
• Never drive a socket S pin from an externally powered 5 V source while EXT_5V is off. The AHCT1G125 is not Ioff-specified: with VCC = 0 its output absolute maximum is VCC + 0.5 = 0.5 V (SCLS378P Section 5.1). Kit modules powered from the socket V pin cannot violate this by construction — the hazard is only externally powered wiring.
• Kit-module pinout is not standardized: J2–J5 are 1 S, 2 V, 3 G, matching the common S/V/G order, but some clone modules swap V and G. Check the module silkscreen before plugging.
• The AHCT output is rated ±8 mA (±25 mA absolute max continuous). Kit LED and relay-driver modules carry their own resistors/transistors; do not hang a bare LED or a shorted long lead on S in output mode.
• Earth-referenced oscilloscope grounds clip only to board GND (shared by the PMOD host and J6 supply — confirm the two supplies share ground before first power in the standalone context).
• Set each channel's jumper for the module actually plugged in. The default (1-2, input) is the safe direction for an unknown module.
• A working level shift is not a timing, EMC, or drive-strength qualification for every kit module; this adapter is unverified hardware.

3. Power and control sequence#

The board has two rails with no supervisor; sequencing is defined by the gate datasheets, and the two parts behave differently with one rail down.

1. 3V3 and GND arrive on PMOD pins 6/12 and 5/11 (C5–C8 100 nF per LVC gate, C10 10 µF bulk). EXT_5V and GND arrive on J6 (C1–C4 100 nF per AHCT gate, C9 10 µF bulk). Kit modules draw from EXT_5V on the socket V pins.
2. Each JPn (bridged 1-2 by default) grounds DIRn_RX, enabling the LVC receive gate; DIRn_TX sits at EXT_5V through its 10 kΩ, so the AHCT drive gate is Hi-Z. Bridging 2-3 instead swaps the two roles. There is no power-up race: the enables are resistor/jumper-static.
3. EXT_5V present, 3V3 absent. The LVC gates are unpowered but are explicitly rated for this: Ioff supports partial-power-down, and both the input and the Hi-Z/power-off output may sit at up to 5.5 V with VCC = 0 while leaking at most ±10 µA (SCES223T Sections 7.1/7.5). A powered kit sensor may therefore drive S at 5 V with no back-feed into the dead 3V3 rail beyond microamps. Caution for output-mode channels: the AHCT is powered and enabled, but its input CHn floats if the host is unpowered (no pull-up/down exists on the CHn nets), so S is undefined and can chatter a connected actuator. Floating inputs on a powered CMOS gate also violate the datasheet note requiring unused inputs at VCC or GND.
4. 3V3 present, EXT_5V absent. The AHCT gates are unpowered and are NOT Ioff-specified; their power-off output limit is 0.5 V. This is safe by construction because everything that legitimately drives S (the kit module) is also powered from EXT_5V, so S rests at 0 V through its 100 kΩ. The AHCT input is safe: its input rating (5.5 V recommended, 7 V absolute) is independent of VCC and input leakage is specified at ±1 µA over VCC = 0–5.5 V, so the FPGA may drive CHn freely with the 5 V rail down. The LVC gates work normally; an input-mode channel simply reports S = low.
5. Both rails present. In input mode the kit module drives S at 5 V logic, the LVC translates to 3.3 V CMOS, and Rn (100 Ω) carries it to the PMOD (module-driven-line rule). In output mode the FPGA's 3.3 V logic feeds the AHCT directly — its TTL thresholds (VIH 2.0 V fixed) are why AHCT and not AHC is used — and the AHCT re-drives S at 5 V CMOS levels.
6. Recommended order: apply 3V3 (and configure the FPGA) before or together with EXT_5V when any channel is in output mode, so actuators never see a floating-input AHCT. Input-mode-only configurations are order-insensitive. Section 9.B tests both orders.

4. Interfaces and pin maps#

Both gate packages are SOT-23-5 (DBV) with the same pinout (SCLS378P Table 4-1; SCES223T Section 6): 1 = ~OE, 2 = A (input), 3 = GND, 4 = Y (output), 5 = VCC — convenient for probing, dangerous for mix-ups (see Section 8).

Per-channel direction jumper truth table#

JPn pad 2 is the common and is tied to GND; pad 1 is DIRn_RX (LVC ~OE, pulled to 3V3 by R(n+8) 10 kΩ); pad 3 is DIRn_TX (AHCT ~OE, pulled to EXT_5V by R(n+4) 10 kΩ). The factory-default footprint is bridged 1-2.

Contention is impossible by construction in every legal jumper state: grounding an ~OE requires bridging its pad to the single common GND pad, and one solder bridge can only reach one side while the other side's dedicated 10 kΩ holds it disabled at its rail. The one physical defeat is an illegal 1-2-3 triple solder bridge, which grounds both enables at once — that creates a CHn→AHCT→Sn→LVC→CHn feedback loop plus contention with whatever external device drives Sn or CHn. It is an assembly defect, not a usable state; Section 8 makes inspecting for it mandatory and Section 9.E verifies Hi-Z behavior in both positions.

Note also what "contention" means here: the two buffers drive different nets (AHCT drives Sn, LVC drives CHn_RX), so the pairs actually protected by the complementary enables are AHCT-vs-kit-module on Sn, and LVC-vs-FPGA on CHn (the latter additionally limited by Rn = 100 Ω).

5. Component-by-component review#

Every reference designator in generate_design.py appears below. JP1–JP4 are solder-jumper footprints excluded from BOM and placement files (in_bom=False, in_pos=False); #FLG01–#FLG03 are ERC power-flag pseudo-components with no physical footprint, listed for completeness. Ranges share one row where the four channels are identical.

6. Datasheet summary and design interpretation#

Consulted (both fetched and read in full):

• TI SN74AHCT1G125 datasheet SCLS378P (August 1997 – revised March 2024), <https://www.ti.com/lit/ds/symlink/sn74ahct1g125.pdf>, product page <https://www.ti.com/product/SN74AHCT1G125>.
• TI SN74LVC1G125 datasheet SCES223T (April 1999 – revised October 2014), <https://www.ti.com/lit/ds/symlink/sn74lvc1g125.pdf>, product page <https://www.ti.com/product/SN74LVC1G125>.

The TXS0108E needs no datasheet here: the binding review finding removed it from the design, and generate_design.py contains no TXS part.

Check the latest datasheet revisions before procurement.

7. Expected values before bench testing#

Targets assume 3V3 = 3.300 V, EXT_5V = 5.000 V, all four JPn bridged 1-2 (default) unless stated. All are design targets calculated from SCLS378P / SCES223T limits, not measured results.

Leakage note: the 0.75 V worst-case Sn idle bound uses both parts' full-temperature-range maximum leakages simultaneously and sits only 50 mV below the LVC VIL of 0.8 V. At room temperature real leakage is orders of magnitude lower and Sn will read millivolts; but this corner is why R13–R16 must not be increased above 100 kΩ, and it is worth measuring on the first article warm.

8. Manual schematic and assembly review checklist#

• Verify U1–U4 are SN74AHCT1G125DBVR and U5–U8 are SN74LVC1G125DBVR by package marking. The two parts share the SOT-23-5 pinout, so a swap is invisible to continuity testing; the AHCT-at-3.3 V swap runs the part below its 4.5 V minimum supply.
• Confirm gate orientation on all eight SOT-23-5 parts (pin 1 = ~OE).
• Inspect all four JPn jumpers: exactly one bridge each (1-2 as shipped); explicitly check no jumper has all three pads bridged — that is the only route to simultaneous enable/contention.
• Measure R5–R8 = 10 k from each JPn pad 3 to EXT_5V, R9–R12 = 10 k from each JPn pad 1 to 3V3, R13–R16 = 100 k from each socket pin 1 to GND, R1–R4 = 100 Ω from each PMOD signal pin to the corresponding LVC pin 4.
• Confirm socket order on J2–J5: pin 1 S, pin 2 EXT_5V, pin 3 GND; buzz pin 2 of all four sockets to J6 pin 1.
• Confirm J6 polarity marking on silkscreen matches pin 1 = +5 V.
• Confirm no continuity between EXT_5V and 3V3 (should be open, both polarities).
• Check decoupling placement in layout review: C1–C4 at U1–U4 VCC (pin 5), C5–C8 at U5–U8 pin 5 (layout not yet started — carry forward).
• Confirm PMOD pins 7–10 really are unconnected.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Record board serial, host identity, measured rail voltages, jumper states, and the kit modules used (with photos — clone modules vary).

Two bench contexts are used throughout. Context (a) — PMOD host: an ECP5/ULX3S-class FPGA board supplies 3V3 on a PMOD port and a test bitstream drives/reads CH1–CH4; EXT_5V comes from a current-limited bench supply on J6 sharing the host's ground. Context (b) — standalone: two current-limited bench supplies (3.3 V ≤ 100 mA, 5.0 V ≤ 500 mA, common ground), a 3.3 V logic source (function generator at 3.3 Vpp offset 1.65 V, or a Pico GPIO) for CHn, a 5 V logic source for Sn, and a scope.

A. Unpowered inspection and resistance tests#

1. Complete the Section 8 checklist under magnification.
2. Measure 3V3-to-GND and EXT_5V-to-GND resistance in both polarities; investigate < 1 kΩ. Confirm EXT_5V-to-3V3 is open.
3. Confirm each Sn reads ≈ 100 kΩ to GND and each CHn reads ≈ 100 Ω to its LVC output pin.

B. First power and rail-sequencing tests (no modules, no host traffic)#

Perform in context (b) first; repeat step 1 in context (a).

1. Apply both rails. Currents in the Section 7 quiescent bands; DIRn voltages per Section 7; every Sn ≈ 0 V; every CHn low (input mode: LVC drives the low Sn state through Rn).
2. Sequencing order 1 — EXT_5V only, 3V3 off (disconnected). Expect: EXT_5V current still in band; the 3V3 rail node rises to < 0.1 V (LVC Ioff limits cross-feed to ≤ 10 µA per channel); Sn ≈ 0 V. Then connect 3V3 with the supply already on: no current spike beyond C10 charging, levels settle to step 1 values.
3. Sequencing order 2 — 3V3 only, EXT_5V off. Expect: 3V3 current in band; the EXT_5V node stays < 0.1 V; Sn ≈ 0 V (nothing may drive it — AHCT power-off output limit, Section 2); CHn low. Then apply EXT_5V: levels settle to step 1 values.
4. Move one channel's jumper to 2-3 (output mode) and repeat steps 2–3 for that channel. With EXT_5V on and 3V3/host absent, note Sn is undefined (floating AHCT input) — observe it on the scope and record the behavior; this confirms the Section 3 caution rather than a pass/ fail level. Restore the jumper.

C. Input-mode channel test (JPn 1-2)#

Context (b), then context (a) with the FPGA reading CHn.

1. Drive Sn (socket pin 1) from the 5 V logic source. Static: Sn = 5 V → CHn ≥ 3.2 V; Sn = 0 V → CHn ≤ 0.1 V.
2. Threshold margin: set Sn = 2.4 V (worst-case TTL-high sensor) → CHn must read high; Sn = 0.8 V → CHn low.
3. Square wave 100 kHz on Sn: clean 3.3 V swing on CHn, monotonic edges (scope at the PMOD pin, 10x probe).
4. Repeat for all four channels. In context (a), the FPGA test design reports each CHn level (LEDs or UART).

D. Output-mode channel test (JPn 2-3)#

1. Drive CHn from the 3.3 V logic source (context b) or the FPGA (context a). Static: CHn = 3.3 V → Sn ≥ 4.4 V; CHn = 0 V → Sn ≤ 0.1 V.
2. Loaded: sink 8 mA from Sn (620 Ω to GND while high): Sn ≥ 3.94 V. Source 8 mA (620 Ω to EXT_5V while low): Sn ≤ 0.36 V.
3. Slow-ramp CHn 0 → 3.3 V: Sn must switch once, between 0.8 V and 2.0 V, without oscillation (TTL threshold check).
4. Square wave 100 kHz on CHn: full 0/5 V swing on Sn, controlled edges into a 1 m test lead + 1 kΩ load (the TXS0108E failure case this design exists to avoid).
5. Restore the jumper to 1-2 after each channel unless the final configuration is output mode.

E. Contention-impossibility / Hi-Z verification (both jumper positions)#

This test demonstrates the disabled gate is genuinely Hi-Z in each mode, with the enabled side driving both states.

1. JPn 1-2 (LVC enabled, AHCT must be Hi-Z). Drive Sn externally to 5 V, then to 0 V, through a 10 kΩ series resistor from the 5 V logic source. Measure the voltage across that 10 kΩ: it must correspond to only the 100 kΩ pull-down plus microamp leakage (high state: Sn ≥ ~4.4 V, i.e. ≤ ~60 µA total including 50 µA through R(n+12); low state: ≈ 0 µA). Any milliamp-scale current means the AHCT is driving — inspect JPn for a triple bridge, DIRn_TX voltage, and U-part identity.
2. JPn 2-3 (AHCT enabled, LVC must be Hi-Z). Drive CHn high and low from the host/source and measure the voltage across Rn (100 Ω, between CHn and the LVC output). It must be ≤ ~1 mV in both states (≤ 10 µA IOZ). A measurable drop means the LVC is driving against the source — same inspection list.
3. Confirm the constructional argument on the board itself: with the DMM, verify in each position that exactly one of DIRn_TX/DIRn_RX is at 0 V and the other is at its rail (Section 7 table). Both at 0 V is the illegal triple-bridge state; both at their rails with a bridge fitted means an open joint.
4. Jumper-open state: remove the bridge on one channel, verify Sn ≈ 0 V, CHn floats (scope shows it following probe leakage), and both DIRn nets sit at their rails. Re-bridge 1-2.

F. Kit-module smoke test (one real module in each direction)#

Use genuine 37-in-1-class modules; record exact module identity and silkscreen pinout. Verify each module's V/G order against the socket before plugging (Section 2).

1. 5 V sensor → FPGA (input mode, JPn 1-2). Plug a 5 V digital-output sensor module — e.g. a KY-032/obstacle or PIR module, or the simple button module — into J2. Pass criteria: with EXT_5V on, the module's S output toggles Sn between ≥ 2.4 V and ≤ 0.8 V (per the module), CHn follows with ≥ 3.2 V / ≤ 0.1 V levels, and the FPGA (context a) registers every state change over 20 manual triggers with zero missed or spurious events.
2. FPGA → 5 V actuator (output mode, JPn 2-3). Plug a kit LED module (KY-016 class) or a 5 V relay module into J3. Pass criteria: the FPGA toggling CHn at 1 Hz visibly switches the module with no flicker, chatter, or missed cycles over 60 s; Sn shows ≥ 4.4 V / ≤ 0.4 V under the module's load; EXT_5V current matches the module's rating; a relay module's coil kick does not disturb Sn beyond a brief edge (scope).
3. Run both channels simultaneously (sensor in, actuator out) for 10 min: no cross-channel interference on the scope, rails within 5%.

G. Signal-integrity and configuration spot checks#

1. Scope rise/fall at Sn (output mode) and CHn (input mode) at 100 kHz with a real module attached; record 10–90% times as the baseline for future revisions (no pass limit — kit signals are slow).
2. Exercise all 16 jumper-configuration combinations? No — that is 2^4 with identical independent channels; instead verify each channel once in each mode (already done in C/D) and record final shipped positions.
3. Long-lead abuse test: 1 m of ribbon on a socket in each mode; signals must remain monotonic at the receiver thresholds.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The architecture directly answers the review finding that killed the TXS0108E: with direction known per socket, two fixed-direction single gates with complementary, jumper-selected enables give full-strength, edge-controlled drive in each direction and make contention structurally impossible in every legal jumper state — the single GND common pad can only reach one enable, and the other is held disabled by its own 10 kΩ. The AHCT/LVC pairing is the right one: the AHCT's fixed TTL input thresholds accept 3.3 V logic into a 5 V-rail driver, and the LVC's 5 V-tolerant, Ioff-protected input receives 5 V signals and survives partial power-down without back-feeding the PMOD rail. The 100 Ω module-driven-line resistors, per-gate decoupling, per-socket idle pull-downs, and the strict EXT_5V-from-J6-only rule all follow the line patterns, and ERC is clean.

The open risks are real and should be carried into layout and first bench: no PCB exists yet (placement, EXT_5V distribution to four sockets, and decoupling proximity unverified); the CHn nets have no pull devices, so an output-mode AHCT has a floating input whenever the host is unpowered or unconfigured — undefined actuator drive that only operating procedure currently mitigates; the illegal 1-2-3 solder bridge on any JPn defeats the contention guarantee and must be an explicit inspection item forever; the two gate types share a pinout, making a part mix-up invisible except by marking inspection (and the AHCT-at-3.3 V direction of the swap is out of spec); J6 has no reverse- polarity or overvoltage protection; the worst-case Hi-Z-leakage budget against the 100 kΩ pull-down leaves only ~50 mV to the LVC VIL corner at temperature extremes; socket and screw-terminal MPNs are still TBD; and every number in Section 7 is calculated from SCLS378P/SCES223T rather than measured on hardware.